Description
Transfers the source operand to the destination.

Operation

void MOV (int m, int n)
{
  R[n] = R[m];
  PC += 2;
}

Description
Stores immediate data, sign-extended to longword, in general register Rn.

Operation

void MOVI (int i, int n)
{
  if ((i & 0x80) == 0)
    R[n] = (0x000000FF & i);
  else
    R[n] = (0xFFFFFF00 | i);

  PC += 2;
}

Description
Stores immediate data that has been sign-extended to longword in general register Rn.


Operation

void MOVI20 (int i, int n)
{
  if (i & 0x00080000) == 0)
    R[n] = (0x000FFFFF & (long)i);
  else
    R[n] = (0xFFF00000 | (long)i);

  PC += 4;
}

Description
Shifts immediate data 8 bits to the left and performs sign extension to longword, then stores the resulting data in general register Rn. Using an OR or ADD instruction as the next instruction enables a 28-bit absolute address to be generated.


Operation

void MOVI20S (int i, int n)
{
  if (i & 0x00080000) == 0)
    R[n] = (0x000FFFFF & (long)i);
  else
    R[n] = (0xFFF00000 | (long)i);

  R[n] <<= 8;
  PC += 4;
}

Description
Stores the effective address of the source operand into general register R0. The 8-bit displacement is zero-extended and quadrupled. Consequently, the relative interval from the operand is PC + 1020 bytes. The PC is the address four bytes after this instruction, but the lowest two bits of the PC are fixed at 00.

Note
SH1*, SH2*, SH3*:
If this instruction is placed immediately after a delayed branch instruction, the PC must point to an address specified by (the starting address of the branch destination) + 2.

SH4*:
If this instruction is executed in a delay slot, a slot illegal instruction exception will be generated.

Operation

void MOVA (int d)
{
  unsigned int disp;
  disp = (unsigned int)(0x000000FF & d);
  R[0] = (PC & 0xFFFFFFFC) + 4 + (disp << 2);
  PC += 2;
}

Possible Exceptions

Slot illegal instruction

Description
Stores immediate data, sign-extended to longword, in general register Rn. The data is stored from memory address (PC + 4 + displacement * 2). The 8-bit displacement is multiplied by two after zero-extension, and so the relative distance from the table is in the range up to PC + 4 + 510 bytes. The PC value is the address of this instruction.

Note
If the following instruction is a branch instruction, it is identified as a slot illegal instruction.

Operation

void MOVWI (int d, int n)
{
  unsigned int disp = (0x000000FF & d);
  R[n] = Read_16 (PC + 4 + (disp << 1));
  if ((R[n] & 0x8000) == 0)
    R[n] &= 0x0000FFFF;
  else
    R[n] |= 0xFFFF0000;

  PC += 2;
}

Possible Exceptions

Data TLB multiple-hit exception

Slot illegal instruction exception

Data TLB miss exception

Data TLB protection violation exception

Description
Stores immediate data, sign-extended to longword, in general register Rn. The data is stored from memory address (PC + 4 + displacement * 4). The 8-bit displacement is multiplied by four after zero-extension, and so the relative distance from the operand is in the range up to PC + 4 + 1020 bytes. The PC value is the address of this instruction. A value with the lower 2 bits adjusted to 00 is used in address calculation.

Note
If the following instruction is a branch instruction, it is identified as a slot illegal instruction.

Operation

void MOVLI (int d, int n)
{
  unsigned int disp = (0x000000FF & d);
  R[n] = Read_32 ((PC & 0xFFFFFFFC) + 4 + (disp << 2));
  PC += 2;
}

Possible Exceptions

Data TLB multiple-hit exception

Slot illegal instruction exception

Data TLB miss exception

Data TLB protection violation exception

Description
Transfers the source operand to the destination. The loaded data is sign-extended to 32 bit before being stored in the destination register.

Operation

void MOVBL (int m, int n)
{
  R[n] = Read_8 (R[m]);
  if ((R[n] & 0x80) == 0)
    R[n] &= 0x000000FF;
  else
    R[n] |= 0xFFFFFF00;

  PC += 2;
}

Possible Exceptions

Data TLB multiple-hit exception

Data TLB miss exception

Data TLB protection violation exception

Data address error

Description
Transfers the source operand to the destination. The loaded data is sign-extended to 32 bit before being stored in the destination register.

Operation

void MOVWL (int m, int n)
{
  R[n] = Read_16 (R[m]);
  if ((R[n] & 0x8000) == 0)
    R[n] &= 0x0000FFFF;
  else
    R[n] |= 0xFFFF0000;

  PC += 2;
}

Possible Exceptions

Data TLB multiple-hit exception

Data TLB miss exception

Data TLB protection violation exception

Data address error

Description
Transfers the source operand to the destination.

Operation

void MOVLL (int m, int n)
{
  R[n] = Read_32 (R[m]);
  PC += 2;
}

Possible Exceptions

Data TLB multiple-hit exception

Data TLB miss exception

Data TLB protection violation exception

Data address error

Description
Transfers the source operand to the destination.

Operation

void MOVBS (int m, int n)
{
  Write_8 (R[n], R[m]);
  PC += 2;
}

Possible Exceptions

Data TLB multiple-hit exception

Data TLB miss exception

Data TLB protection violation exception

Data address error

Initial page write exception

Description
Transfers the source operand to the destination.

Operation

void MOVWS (int m, int n)
{
  Write_16 (R[n], R[m]);
  PC += 2;
}

Possible Exceptions

Data TLB multiple-hit exception

Data TLB miss exception

Data TLB protection violation exception

Data address error

Initial page write exception

Description
Transfers the source operand to the destination.

Operation

void MOVLS (int m, int n)
{
  Write_32 (R[n], R[m]);
  PC += 2;
}

Possible Exceptions

Data TLB multiple-hit exception

Data TLB miss exception

Data TLB protection violation exception

Data address error

Initial page write exception

Description
Transfers the source operand to the destination. The loaded data is sign-extended to 32 bit before being stored in the destination register.

Operation

void MOVBP (int m, int n)
{
  R[n] = Read_8 (R[m]);
  if ((R[n] & 0x80) == 0)
    R[n] &= 0x000000FF;
  else
    R[n] |= 0xFFFFFF00;

  if (n != m)
    R[m] += 1;

  PC += 2;
}

Possible Exceptions

Data TLB multiple-hit exception

Data TLB miss exception

Data TLB protection violation exception

Data address error

Description
Transfers the source operand to the destination. The loaded data is sign-extended to 32 bit before being stored in the destination register.

Operation

void MOVWP (int m, int n)
{
  R[n] = Read_16 (R[m]);
  if ((R[n] & 0x8000) == 0)
    R[n] &= 0x0000FFFF;
  else
    R[n] |= 0xFFFF0000;

  if (n != m)
    R[m] += 2;

  PC += 2;
}

Possible Exceptions

Data TLB multiple-hit exception

Data TLB miss exception

Data TLB protection violation exception

Data address error

Description
Transfers the source operand to the destination.

Operation

void MOVLP (int m, int n)
{
  R[n] = Read_32 (R[m]);

  if (n != m)
    R[m] += 4;

  PC += 2;
}

Possible Exceptions

Data TLB multiple-hit exception

Data TLB miss exception

Data TLB protection violation exception

Data address error

Description
Transfers the source operand to the destination.

Operation

void MOVBM (int m, int n)
{
  Write_8 (R[n] - 1, R[m]);
  R[n] -= 1;
  PC += 2;
}

Possible Exceptions

Data TLB multiple-hit exception

Data TLB miss exception

Data TLB protection violation exception

Data address error

Initial page write exception

Description
Transfers the source operand to the destination.

Operation

void MOVWM (int m, int n)
{
  Write_16 (R[n] - 2, R[m]);
  R[n] -= 2;
  PC += 2;
}

Possible Exceptions

Data TLB multiple-hit exception

Data TLB miss exception

Data TLB protection violation exception

Data address error

Initial page write exception

Description
Transfers the source operand to the destination.

Operation

void MOVLM (int m, int n)
{
  Write_32 (R[n] - 4, R[m]);
  R[n] -= 4;
  PC += 2;
}

Possible Exceptions

Data TLB multiple-hit exception

Data TLB miss exception

Data TLB protection violation exception

Data address error

Initial page write exception

Description
Transfers the source operand to the destination. The loaded data is sign-extended to 32 bit before being stored in the destination register.

Operation

void MOVRSBM (int m)
{
  R[m] -= 1;
  R[0] = Read_16 (R[m]);

  if ((R[0] & 0x80) == 0)
    R[0] &= 0x000000FF;
  else
    R[0] |= 0xFFFFFF00;

  PC+=2;
}

Possible Exceptions

Data address error

Description
Transfers the source operand to the destination. The loaded data is sign-extended to 32 bit before being stored in the destination register.

Operation

void MOVRSWM (int m)
{
  R[m]-= 2;
  R[0] = Read_16 (R[m]);

  if ((R[0] & 0x8000) == 0)
    R[0] &= 0x0000FFFF;
  else
    R[0] |= 0xFFFF0000;

  PC += 2;
}

Possible Exceptions

Data address error

Description
Transfers the source operand to the destination.

Operation

void MOVRSLM (int m)
{
  R[m] -= 4;
  R[0] = Read_32 (R[m]);
  PC += 2;
}

Possible Exceptions

Data address error

Description
Transfers the source operand to the destination.

Operation

void MOVRSBP (int n)
{
  Write_8 (R[n], R[0]);
  R[n] += 1;
  PC += 2;
}

Possible Exceptions

Data address error

Description
Transfers the source operand to the destination.

Operation

void MOVRSWP (int n)
{
  Write_16 (R[n], R[0]);
  R[n] += 2;
  PC += 2;
}

Possible Exceptions

Data address error

Description
Transfers the source operand to the destination.

Operation

void MOVRSLP (int n)
{
  Write_32 (R[n], R[0]);
  R[n] += 4;
  PC += 2;
}

Possible Exceptions

Data address error

Description
Transfers the source operand to the destination. The 4-bit displacement is only zero-extended, so a range up to +15 bytes can be specified. If a memory operand cannot be reached, the @(R0,Rn) mode can be used instead. The loaded data is sign-extended to 32 bit before being stored in the destination register.

Operation

void MOVBL4 (int m, int d)
{
  long disp = (0x0000000F & (long)d);
  R[0] = Read_8 (R[m] + disp);

  if ((R[0] & 0x80) == 0)
    R[0] &= 0x000000FF;
  else
    R[0] |= 0xFFFFFF00;

  PC += 2;
}

Possible Exceptions

Data TLB multiple-hit exception

Data TLB miss exception

Data TLB protection violation exception

Data address error

Description
Transfers the source operand to the destination. This instruction is ideal for data access in a structure or the stack. The loaded data is sign-extended to 32 bit before being stored in the destination register.

Operation

void MOVBL12 (int d, int m, int n)
{
  long disp = (0x00000FFF & (long)d);
  R[n] = Read_8 (R[m] + disp);

  if ((R[n] & 0x80) == 0)
    R[n] &= 0x000000FF;
  else
    R[n] |= 0xFFFFFF00;

  PC += 4;
}

Possible Exceptions

Data address error

Description
Transfers a source operand to a destination, performing unsigned data transfer. This instruction is ideal for data access in a structure or the stack. The loaded data is zero-extended to 32 bit before being stored in the destination register.

Operation

void MOVBUL12 (int d, int m, int n)
{
  long disp = (0x00000FFF & (long)d);
  R[n] = Read_8 (R[m] + disp);
  R[n] &= 0x000000FF;
  PC += 4;
}

Description
Transfers the source operand to the destination. The 4-bit displacement is multiplied by two after zero-extension, enabling a range up to +30 bytes to be specified. If a memory operand cannot be reached, the @(R0,Rn) mode can be used instead. The loaded data is sign-extended to 32 bit before being stored in the destination register.

Operation

void MOVWL4 (int m, int d)
{
  long disp = (0x0000000F & (long)d);
  R[0] = Read_16 (R[m] + (disp << 1));

  if ((R[0] & 0x8000) == 0)
    R[0] &= 0x0000FFFF;
  else
    R[0] |= 0xFFFF0000;

  PC += 2;
}

Possible Exceptions

Data TLB multiple-hit exception

Data TLB miss exception

Data TLB protection violation exception

Data address error

Description
Transfers the source operand to the destination. This instruction is ideal for data access in a structure or the stack. The loaded data is sign-extended to 32 bit before being stored in the destination register.

Operation

void MOVWL12 (int d, int m, int n)
{
  long disp = (0x00000FFF & (long)d);
  R[n] = Read_16 (R[m] + (disp << 1));

  if ((R[n] & 0x8000) == 0)
    R[n] &= 0x0000FFFF;
  else
    R[n] |= 0xFFFF0000;

  PC += 4;
}

Possible Exceptions

Data address error

Description
Transfers a source operand to a destination, performing unsigned data transfer. This instruction is ideal for data access in a structure or the stack. The loaded data is zero-extended to 32 bit before being stored in the destination register.

Operation

void MOVWUL12 (int d, int m, int n)
{
  long disp = (0x00000FFF & (long)d);
  R[n] = Read_16 (R[m] + (disp << 1));
  R[n] &= 0x0000FFFF;
  PC += 4;
}

Description
Transfers the source operand to the destination. The 4-bit displacement is multiplied by four after zero-extension, enabling a range up to +60 bytes to be specified. If a memory operand cannot be reached, the @(R0,Rn) mode can be used instead.

Operation

void MOVLL4 (int m, int d, int n)
{
  long disp = (0x0000000F & (long)d);
  R[n] = Read_32 (R[m] + (disp << 2));
  PC += 2;
}

Possible Exceptions

Data TLB multiple-hit exception

Data TLB miss exception

Data TLB protection violation exception

Data address error

Description
Transfers the source operand to the destination. This instruction is ideal for data access in a structure or the stack.

Operation

void MOVLL12 (int d, int m, int n)
{
  long disp = (0x00000FFF & (long)d);
  R[n] = Read_32 (R[m] + (disp << 2));
  PC += 4;
}

Possible Exceptions

Data address error

Description
Transfers the source operand to the destination. The 4-bit displacement is only zero-extended, so a range up to +15 bytes can be specified. If a memory operand cannot be reached, the @(R0,Rn) mode can be used instead.

Operation

void MOVBS4 (int d, int n)
{
  long disp = (0x0000000F & (long)d);
  Write_8 (R[n] + disp, R[0]);
  PC += 2;
}

Possible Exceptions

Data TLB multiple-hit exception

Data TLB miss exception

Data TLB protection violation exception

Data address error

Initial page write exception

Description
Transfers the source operand to the destination. This instruction is ideal for data access in a structure or the stack.

Operation

void MOVBS12 (int d, int m, int n)
{
  long disp = (0x00000FFF & (long)d);
  Write_8 (R[n] + disp, R[m]);
  PC += 4;
}

Possible Exceptions

Data address error

Description
Transfers the source operand to the destination. The 4-bit displacement is multiplied by two after zero-extension, enabling a range up to +30 bytes to be specified. If a memory operand cannot be reached, the @(R0,Rn) mode can be used instead.

Operation

void MOVWS4 (int d, int n)
{
  long disp = (0x0000000F & (long)d);
  Write_16 (R[n] + (disp << 1), R[0]);
  PC += 2;
}

Possible Exceptions

Data TLB multiple-hit exception

Data TLB miss exception

Data TLB protection violation exception

Data address error

Initial page write exception

Description
Transfers the source operand to the destination. This instruction is ideal for data access in a structure or the stack.

Operation

void MOVWS12 (int d, int m, int n)
{
  long disp = (0x00000FFF & (long)d);
  Write_16 (R[n] + (disp << 1), R[m]);
  PC += 4;
}

Possible Exceptions

Data address error

Description
Transfers the source operand to the destination. The 4-bit displacement is multiplied by four after zero-extension, enabling a range up to +60 bytes to be specified. If a memory operand cannot be reached, the @(R0,Rn) mode can be used instead.

Operation

void MOVLS4 (int m, int d, int n)
{
  long disp = (0x0000000F & (long)d);
  Write_32 (R[n] + (disp << 2), R[m]);
  PC += 2;
}

Possible Exceptions

Data TLB multiple-hit exception

Data TLB miss exception

Data TLB protection violation exception

Data address error

Initial page write exception

Description
Transfers the source operand to the destination. This instruction is ideal for data access in a structure or the stack.

Operation

void MOVLS12 (int d, int m, int n)
{
  long disp = (0x00000FFF & (long)d);
  Write_32 (R[n] + (disp << 2), R[m]);
  PC += 4;
}

Possible Exceptions

Data address error

Description
Transfers the source operand to the destination. The loaded data is sign-extended to 32 bit before being stored in the destination register.

Operation

void MOVBL0 (int m, int n)
{
  R[n] = Read_8 (R[m] + R[0]);

  if ((R[n] & 0x80) == 0)
    R[n] &= 0x000000FF;
  else R[n] |= 0xFFFFFF00;

  PC += 2;
}

Possible Exceptions

Data TLB multiple-hit exception

Data TLB miss exception

Data TLB protection violation exception

Data address error

Description
Transfers the source operand to the destination. The loaded data is sign-extended to 32 bit before being stored in the destination register.

Operation

void MOVWL0 (int m, int n)
{
  R[n] = Read_16 (R[m] + R[0]);

  if ((R[n] & 0x8000) == 0)
    R[n] &= 0x0000FFFF;
  else
    R[n] |= 0xFFFF0000;

  PC += 2;
}

Possible Exceptions

Data TLB multiple-hit exception

Data TLB miss exception

Data TLB protection violation exception

Data address error

Description
Transfers the source operand to the destination.

Operation

void MOVLL0 (int m, int n)
{
  R[n] = Read_32 (R[m] + R[0]);
  PC += 2;
}

Possible Exceptions

Data TLB multiple-hit exception

Data TLB miss exception

Data TLB protection violation exception

Data address error

Description
Transfers the source operand to the destination.

Operation

void MOVBS0 (int m, int n)
{
  Write_8 (R[n] + R[0], R[m]);
  PC += 2;
}

Possible Exceptions

Data TLB multiple-hit exception

Data TLB miss exception

Data TLB protection violation exception

Data address error

Initial page write exception

Description
Transfers the source operand to the destination.

Operation

void MOVWS0 (int m, int n)
{
  Write_16 (R[n] + R[0], R[m]);
  PC += 2;
}

Possible Exceptions

Data TLB multiple-hit exception

Data TLB miss exception

Data TLB protection violation exception

Data address error

Initial page write exception

Description
Transfers the source operand to the destination.

Operation

void MOVLS0 (int m, int n)
{
  Write_32 (R[n] + R[0], R[m]);
  PC += 2;
}

Possible Exceptions

Data TLB multiple-hit exception

Data TLB miss exception

Data TLB protection violation exception

Data address error

Initial page write exception

Description
Transfers the source operand to the destination. The 8-bit displacement is only zero-extended, so a range up to +255 bytes can be specified. The loaded data is sign-extended to 32 bit before being stored in the destination register.

Operation

void MOVBLG (int d)
{
  unsigned int disp = (0x000000FF & d);
  R[0] = Read_8 (GBR + disp);

  if ((R[0] & 0x80) == 0)
    R[0] &= 0x000000FF;
  else
    R[0] |= 0xFFFFFF00;

  PC += 2;
}

Possible Exceptions

Data TLB multiple-hit exception

Data TLB miss exception

Data TLB protection violation exception

Data address error

Description
Transfers the source operand to the destination. The 8-bit displacement is multiplied by two after zero-extension, enabling a range up to +510 bytes to be specified. The loaded data is sign-extended to 32 bit before being stored in the destination register.

Operation

void MOVWLG (int d)
{
  unsigned int disp = (0x000000FF & d);
  R[0] = Read_16 (GBR + (disp << 1));

  if ((R[0] & 0x8000) == 0)
    R[0] &= 0x0000FFFF;
  else
    R[0] |= 0xFFFF0000;

  PC += 2;
}

Possible Exceptions

Data TLB multiple-hit exception

Data TLB miss exception

Data TLB protection violation exception

Data address error

Description
Transfers the source operand to the destination. The 8-bit displacement is multiplied by four after zero-extension, enabling a range up to +1020 bytes to be specified.

Operation

void MOVLLG (int d)
{
  unsigned int disp = (0x000000FF & d);
  R[0] = Read_32 (GBR + (disp << 2));
  PC += 2;
}

Possible Exceptions

Data TLB multiple-hit exception

Data TLB miss exception

Data TLB protection violation exception

Data address error

Description
Transfers the source operand to the destination. The 8-bit displacement is only zero-extended, so a range up to +255 bytes can be specified.

Operation

void MOVBSG (int d)
{
  unsigned int disp = (0x000000FF & d);
  Write_8 (GBR + disp, R[0]);
  PC += 2;
}

Possible Exceptions

Data TLB multiple-hit exception

Data TLB miss exception

Data TLB protection violation exception

Data address error

Initial page write exception

Description
Transfers the source operand to the destination. The 8-bit displacement is multiplied by two after zero-extension, enabling a range up to +510 bytes to be specified.

Operation

void MOVWSG (int d)
{
  unsigned int disp = (0x000000FF & d);
  Write_16 (GBR + (disp << 1), R[0]);
  PC += 2;
}

Possible Exceptions

Data TLB multiple-hit exception

Data TLB miss exception

Data TLB protection violation exception

Data address error

Initial page write exception

Description
Transfers the source operand to the destination. The 8-bit displacement is multiplied by four after zero-extension, enabling a range up to +1020 bytes to be specified.

Operation

void MOVLSG (int d)
{
  unsigned int disp = (0x000000FF & (long)d);
  Write_32 (GBR + (disp << 2), R[0]);
  PC += 2;
}

Possible Exceptions

Data TLB multiple-hit exception

Data TLB miss exception

Data TLB protection violation exception

Data address error

Initial page write exception

Description
MOVCO is used in combination with MOVLI to realize an atomic read-modify-write operation in a single processor.

This instruction copies the value of the LDST flag to the T bit. When the T bit is set to 1, the value of R0 is stored at the address in Rm. If the T bit is cleared to 0, the value is not stored at the address in Rm. Finally, the LDST flag is cleared to 0. Since the LDST flag is cleared by an instruction or exception, storage by the MOVCO instruction only proceeds when no interrupt or exception has occurred between the execution of the MOVLI and MOVCO instructions.

Operation

void MOVCO (int n)
{
  T = LDST;
  if (T == 1)
    Write_32 (R[n], R[0]);

  LDST = 0;
  PC += 2
}

Possible Exceptions

Data TLB multiple-hit exception

Data TLB miss exception

Data TLB protection violation exception

Initial page write exception

Data address error

Description
MOVLI is used in combination with MOVCO to realize an atomic read-modify-write operation in a single processor.

This instruction sets the LDST flag to 1 and reads the four bytes of data indicated by Rm into R0. If, however, an interrupt or exception occurs, LDST is cleared to 0. Storage by the MOVCO instruction only proceeds when the instruction is executed after the LDST bit has been set by the MOVLI instruction and not cleared by an interrupt or other exception. When LDST has been cleared to 0, the MOVCO instruction clears the T bit and does not proceed with storage.

Operation

void MOVLINK (int m)
{
  LDST = 1;
  R[0] = Read_32 (R[m]);
  PC += 2
}

Possible Exceptions

Data TLB multiple-hit exception

Data TLB miss exception

Data TLB protection violation exception

Data address error

Description
Loads the longword of data from the effective address indicated by the contents of Rm in memory to R0. The address is not restricted to longword boundaries address (4n). This instruction allows loading from non-longword-boundary addresses (4n + 1, 4n + 2, and 4n + 3). Data address error exceptions do not occur when access is to non-longword-boundary addresses (4n + 1, 4n + 2, and 4n + 3).

Operation

void MOVUAL (int m)
{
  Read_Unaligned_32 (R0, R[m]);
  PC += 2;
}

Possible Exceptions

Data TLB multiple-hit exception

Data TLB miss exception

Data TLB protection violation exception

Data address error (when the privileged area is accessed from user mode)

Description
Loads the longword of data from the effective address indicated by the contents of Rm in memory to R0. The address is not restricted to longword boundaries address (4n). This instruction allows loading from non-longword-boundary addresses (4n + 1, 4n + 2, and 4n + 3). Data address error exceptions do not occur when access is to non-longword-boundary addresses (4n + 1, 4n + 2, and 4n + 3).

Operation

void MOVUALP (int m)
{
  Read_Unaligned_32 (R0,R[m]);

  if (m != 0)
    R[m] += 4;

  PC += 2;
}

Possible Exceptions

Data TLB multiple-hit exception

Data TLB miss exception

Data TLB protection violation exception

Data address error (when the privileged area is accessed from user mode)

Description
Transfers a source operand to a destination. This instruction performs transfer between a number of general registers (R0 to Rn/Rm) not exceeding the specified register number and memory with the contents of R15 as its address.

If R15 is specified, PR is transferred instead of R15. That is, when nnnn(mmmm) = 1111 is specified, R0 to R14 and PR are the general registers subject to transfer.

Operation

void MOVLMML (int m)
{
  for (int i = m; i >= 0; i--)
  {
    if (i == 15)
      Write_32 (R[15] - 4, PR);
    else
      Write_32 (R[15] - 4, R[i]);

    R[15] -= 4;
  }

  PC += 2;
}

Possible Exceptions

Data address error

Description
Transfers a source operand to a destination. This instruction performs transfer between a number of general registers (R0 to Rn/Rm) not exceeding the specified register number and memory with the contents of R15 as its address.

If R15 is specified, PR is transferred instead of R15. That is, when nnnn(mmmm) = 1111 is specified, R0 to R14 and PR are the general registers subject to transfer.

Operation

void MOVLPML (int n)
{
  for (int i = 0; i <= n; i++)
  {
    if (i == 15)
      PR = Read_32 (R[15]);
    else
      R[i] = Read_32 (R[15]);

    R[15] += 4;
  }

  PC += 2;
}

Possible Exceptions

Data address error

Description
Transfers a source operand to a destination. This instruction performs transfer between a number of general registers (Rn/Rm to R14, PR) not lower than the specified register number and memory with the contents of R15 as its address.

If R15 is specified, PR is transferred instead of R15.

Operation

void MOVLMMU (int m)
{
  Write_32 (R[15] - 4, PR);
  R[15] -= 4;

  for (int i = 14; i >= m; i--)
  {
    Write_32 (R[15] - 4, R[i]);
    R[15] -= 4;
  }

  PC += 2;
}

Possible Exceptions

Data address error

Description
Transfers a source operand to a destination. This instruction performs transfer between a number of general registers (Rn/Rm to R14, PR) not lower than the specified register number and memory with the contents of R15 as its address.

If R15 is specified, PR is transferred instead of R15.

Operation

void MOVLPMU (int n)
{
  for (int i = n; i <= 14; i++)
  {
    R[i] = Read_32 (R[15]);
    R[15] += 4;
  }

  PR = Read_32 (R[15]);
  R[15] += 4;
  PC += 2;
}

Possible Exceptions

Data address error

Description
Reverses the T bit and then stores the resulting value in general register Rn. The value of Rn is 0 when T = 1 and 1 when T = 0.

Operation

void MOVRT (int n)
{
  if (T == 1)
    R[n] = 0x00000000;
  else
    R[n] = 0x00000001;

  PC += 2;
}

Description
Stores the T bit in general register Rn. The value of Rn is 1 when T = 1 and 0 when T = 0.

Operation

void MOVT (int n)
{
  if (T == 1)
    R[n] = 0x00000001;
  else
    R[n] = 0x00000000;
  PC += 2;
}

Description
Inverts the T bit, then stores the resulting value in the T bit.

Operation

void NOTT (void)
{
  if (T == 1)
    T = 0;
  else
    T = 1;

  PC += 2;
}

Description
Swaps the upper and lower parts of the contents of general register Rm and stores the result in Rn. The 8 bits from bit 15 to bit 8 of Rm are swapped with the 8 bits from bit 7 to bit 0. The upper 16 bits of Rm are transferred directly to the upper 16 bits of Rn.

Operation

void SWAPB (int m, int n)
{
  unsigned long temp0, temp1;
  temp0 = R[m] & 0xFFFF0000;
  temp1 = (R[m] & 0x000000FF) << 8;
  R[n] = (R[m] & 0x0000FF00) >> 8;
  R[n] = R[n] | temp1 | temp0;
  PC += 2;
}

Description
Swaps the upper and lower parts of the contents of general register Rm and stores the result in Rn. The 16 bits from bit 31 to bit 16 of Rm are swapped with the 16 bits from bit 15 to bit 0.

Operation

void SWAPW (int m, int n)
{
  unsigned long temp;
  temp = (R[m] >> 16) & 0x0000FFFF;
  R[n] = R[m] << 16;
  R[n] |= temp;
  PC += 2;
}

Description
Extracts the middle 32 bits from the 64-bit contents of linked general registers Rm and Rn, and stores the result in Rn.


Operation

void XTRCT (int m, int n)
{
  unsigned long high = (R[m] << 16) & 0xFFFF0000;
  unsigned long low = (R[n] >> 16) & 0x0000FFFF;
  R[n] = high | low;
  PC += 2;
}

Description
ANDs a specified bit in memory at the address indicated by (disp + Rn) with the T bit, and stores the result in the T bit. The bit number is specified by 3-bit immediate data. With this instruction, data is read from memory as a byte unit.

Operation

void BANDM (int d, int i, int n)
{
  long disp = (0x00000FFF & (long)d);
  long imm = (0x00000007 & (long)i);
  long temp = Read_8 (R[n] + disp);
  long assignbit = (0x00000001 << imm) & temp;

  if ((T == 0) || (assignbit == 0))
    T = 0;
  else
    T = 1;

  PC += 4;
}

Possible Exceptions

Data address error

Description
ANDs the value obtained by inverting a specified bit of memory at the address indicated by (disp + Rn) with the T bit, and stores the result in the T bit. The bit number is specified by 3-bit immediate data. With this instruction, data is read from memory as a byte unit.

Operation

void BANDNOTM (int d, int i, int n)
{
  long disp = (0x00000FFF & (long)d);
  long imm = (0x00000007 & (long)i);
  long temp = Read_8 (R[n] + disp);
  long assignbit = (0x00000001 << imm) & temp;

  if ((T == 1) && (assignbit == 0))
    T = 1;
  else
    T = 0;

  PC += 4;
}

Possible Exceptions

Data address error

Description
Clears a specified bit of memory at the address indicated by (disp + Rn). The bit number is specified by 3-bit immediate data. After data is read from memory as a byte unit, clearing of the specified bit is executed and the resulting data is then written to memory as a byte unit.

Operation

void BCLRM (int d, int i, int n)
{
  long disp = (0x00000FFF & (long)d);
  long imm = (0x00000007 & (long)i);
  long temp = Read_8 (R[n] + disp);
  temp &= (~(0x00000001 < 

Possible Exceptions

Data address error

Description
Clears a specified bit of the LSB 8 bits of a general register Rn. The bit number is specified by 3-bit immediate data.

Operation

void CLR (int i, int n)
{
  long imm, temp;
  imm = (0x00000007 & (long)i);
  R[n] &= (~(0x00000001 << imm));
  PC += 2;
}

Description
Stores a specified bit of memory at the address indicated by (disp + Rn) in the T bit. The bit number is specified by 3-bit immediate data. Data is read from memory as a byte unit.

Operation

void BLDM (int d, int i, int n)
{
  long disp = (0x00000FFF & (long)d);
  long imm = (0x00000007 & (long)i);
  long temp = Read_8 (R[n] + disp);
  long assignbit = (0x00000001 << imm) & temp;

  if (assignbit == 0)
    T = 0;
  else
    T = 1;

  PC += 4;
}

Possible Exceptions

Data address error

Description
Stores a specified bit of the LSB 8 bits of a general register Rn in the T bit. The bit number is specified by 3-bit immediate data.

Operation

void BLD (int i, int n)
{
  long imm, assignbit;
  imm = (0x00000007 & (long)i);
  assignbit = (0x00000001 << imm) & R[n];

  if (assignbit == 0)
    T = 0;
  else
    T = 1;

  PC += 2;
}

Description
Inverts a specified bit of memory at the address indicated by (disp + Rn), and stores the resulting value in the T bit. The bit number is specified by 3-bit immediate data. Data is read from memory as a byte unit.

Operation

void BLDNOTM (int d, int i, int n)
{
  long disp = (0x00000FFF & (long)d);
  long imm = (0x00000007 & (long)i);
  long temp = Read_8 (R[n] + disp);
  long assignbit = (0x00000001 << imm) & temp;

  if (assignbit == 0)
    T = 1;
  else
    T = 0;

  PC += 4;
}

Possible Exceptions

Data address error

Description
ORs a specified bit in memory at the address indicated by (disp + Rn) with the T bit, and stores the result in the T bit. The bit number is specified by 3-bit immediate data. Data is read from memory as a byte unit.

Operation

void BORM (int d, int i, int n)
{
  long disp = (0x00000FFF & (long)d);
  long imm = (0x00000007 & (long)i);
  long temp = Read_8 (R[n] + disp);
  long assignbit = (0x00000001 << imm) & temp;

  if ((T == 0) && (assignbit == 0))
    T = 0;
  else
    T = 1;

  PC += 4;
}

Possible Exceptions

Data address error

Description
ORs the value obtained by inverting a specified bit of memory at the address indicated by (disp + Rn) with the T bit, and stores the result in the T bit. The bit number is specified by 3-bit immediate data. With this instruction, data is read from memory as a byte unit.

Operation

void BORNOTM (int d, int i, int n)
{
  long disp = (0x00000FFF & (long)d);
  long imm = (0x00000007 & (long)i);
  long temp = Read_8 (R[n] + disp);
  long assignbit = (0x00000001 << imm) & temp;

  if ((T == 1) || (assignbit == 0))
    T = 1;
  else
    T = 0;

  PC += 4;
}

Possible Exceptions

Data address error

Description
Sets to 1 a specified bit of memory at the address indicated by (disp + Rn). The bit number is specified by 3-bit immediate data. After data is read from memory as a byte unit, the specified bit is set to 1, and the resulting data is then written to memory as a byte unit.

Operation

void BSETM (int d, int i, int n)
{
  long disp = (0x00000FFF & (long)d);
  long imm = (0x00000007 & (long)i);
  long temp = Read_8 (R[n] + disp);
  temp |= (0x00000001 << imm);
  Write_8 (R[n] + disp, temp);
  PC += 4;
}

Possible Exceptions

Data address error

Description
Sets to 1 a specified bit of the LSB 8 bits of a general register Rn. The bit number is specified by 3-bit immediate data.

Operation

void BSET (int i, int n)
{
  long imm, temp;
  imm = (0x00000007 & (long)i);
  R[n] |= (0x00000001 << imm);
  PC += 2;
}

Description
Transfers the contents of the T bit to a specified 1-bit location of memory at the address indicated by (disp + Rn). The bit number is specified by 3-bit immediate data. After data is read from memory as a byte unit, transfer from the T bit to the specified bit is executed, and the resulting data is then written to memory as a byte unit.

Operation

void BSTM (int d, int i, int n)
{
  long disp = (0x00000FFF & (long)d);
  long imm = (0x00000007 & (long)i);
  long temp = Read_8 (R[n] + disp);

  if (T == 0)
    temp &= (~(0x00000001 << imm));
  else
    temp |= (0x00000001 << imm);

  Write_8 (R[n] + disp, temp);
  PC += 4;
}

Possible Exceptions

Data address error

Description
Transfers the contents of the T bit to a specified 1-bit location of the LSB 8 bits of a general register Rn. The bit number is specified by 3-bit immediate data.

Operation

void BST (int i, int n)
{
  long disp, imm;
  disp = (0x00000FFF & (long)d);
  imm = (0x00000007 & (long)i);

  if (T == 0)
    R[n] &= (~(0x00000001 << imm));
  else
    R[n] |= (0x00000001 << imm);

  PC += 2;
}

Description
Exclusive-ORs a specified bit in memory at the address indicated by (disp + Rn) with the T bit, and stores the result in the T bit. The bit number is specified by 3-bit immediate data. With this instruction, data is read from memory as a byte unit.

Operation

void BXORM (int d, int i, int n)
{
  long disp = (0x00000FFF & (long)d);
  long imm = (0x00000007 & (long)i);
  long temp = Read_8 (R[n] + disp);
  long assignbit = (0x00000001 << imm) & temp;

  if (assignbit == 0)
  {
    if (T == 0)
      T = 0;
    else
      T = 1;
  }
  else
  {
    if (T == 0)
      T = 1;
    else
      T = 0;
  }

  PC += 4;
}

Possible Exceptions

Data address error

Description
Adds together the contents of general registers Rn and Rm and stores the result in Rn.

Operation

void ADD (int m, int n)
{
  R[n] += R[m];
  PC += 2;
}

Description
Adds together the contents of general register Rn and the immediate value and stores the result in Rn. The 8-bit immediate value is sign-extended to 32 bits, which allows it to be used for immediate subtraction or decrement operations.

Operation

void ADDI (int i, int n)
{
  if ((i & 0x80) == 0)
    R[n] += (0x000000FF & (long)i);
  else
    R[n] += (0xFFFFFF00 | (long)i);

  PC += 2;
}

Description
Adds together the contents of general registers Rn and Rm and the T bit, and stores the result in Rn. A carry resulting from the operation is reflected in the T bit. This instruction can be used to implement additions exceeding 32 bits.

Operation

void ADDC (int m, int n)
{
  unsigned long tmp0, tmp1;
  tmp1 = R[n] + R[m];
  tmp0 = R[n];
  R[n] = tmp1 + T;

  if (tmp0>tmp1)
    T = 1;
  else
    T = 0;

  if (tmp1 > R[n])
    T = 1;

  PC += 2;
}

Example

clrt           ! r0:r1 (64 bits) + r2:r3 (64 bits) = r0:r1 (64 bits)
addc  r3,r1    ! Before execution T = 0, r1 = 0x00000001, r3 = 0xFFFFFFFF
               ! After execution T = 1, r1 = 0x00000000
addc  r2,r0    ! Before execution T = 1, r0 = 0x00000000, r2 = 0x00000000
               ! After execution T = 0, r0 = 0x00000001

Description
Adds together the contents of general registers Rn and Rm and stores the result in Rn. If overflow occurs, the T bit is set.

Operation

void ADDV (int m, int n)
{
  long dest, src, ans;

  if ((long)R[n] >= 0)
    dest = 0;
  else
    dest = 1;

  if ((long)R[m] >= 0)
    src = 0;
  else
    src = 1;

  src += dest;
  R[n] += R[m];

  if ((long)R[n] >= 0)
    ans = 0;
  else
    ans = 1;

  ans += dest;

  if (src == 0 || src == 2)
  {
    if (ans == 1)
      T = 1;
    else
      T = 0;
  }
  else
    T = 0;

  PC += 2;
}

Example

addv  r0,r1  ! Before execution: r0 = 0x00000001, r1 = 0x7FFFFFFE, T = 0
             ! After execution:  r1 = 0x7FFFFFFF, T = 0

addv  r0,r1  ! Before execution: r0 = 0x00000002, r1 = 0x7FFFFFFE, T = 0
             ! After execution:  r1 = 0x80000000, T = 1

Description
Compares general register R0 and the sign-extended 8-bit immediate data and sets the T bit if the values are equal. If they are not equal the T bit is cleared. The contents of R0 are not changed.

Operation

void CMPIM (int i)
{
  long imm;

  if ((i & 0x80) == 0)
    imm = (0x000000FF & (long i));
  else
    imm = (0xFFFFFF00 | (long i));

  if (R[0] == imm)
    T = 1;
  else
    T = 0;

  PC += 2;
}

Description
Compares general registers Rn and Rm, and sets the T bit if they are equal. The contents of Rn and Rm are not changed.

Operation

void CMPEQ (int m, int n)
{
  if (R[n] == R[m])
    T = 1;
  else
    T = 0;

  PC += 2;
}

Description
Compares general registers Rn and Rm, and sets the T bit if Rn is greater or equal Rm. The values for the comparison are interpreted as unsigned integer values. The contents of Rn and Rm are not changed.

Operation

void CMPHI (int m, int n)
{
  if ((unsigned long)R[n] >= (unsigned long)R[m])
    T = 1;
  else
    T = 0;

  PC += 2;
}

Description
Compares general registers Rn and Rm, and sets the T bit if Rn is greater or equal Rm. The values for the comparison are interpreted as signed integer values. The contents of Rn and Rm are not changed.

Operation

void CMPGE (int m, int n)
{
  if ((long)R[n] >= (long)R[m])
    T = 1;
  else
    T = 0;

  PC += 2;
}

Description
Compares general registers Rn and Rm, and sets the T bit if Rn is greater Rm. The values for the comparison are interpreted as unsigned integer values. The contents of Rn and Rm are not changed.

Operation

void CMPHI (int m, int n)
{
  if ((unsigned long)R[n] > (unsigned long)R[m])
    T = 1;
  else
    T = 0;

  PC += 2;
}

Description
Compares general registers Rn and Rm, and sets the T bit if Rn is greater Rm. The values for the comparison are interpreted as signed integer values. The contents of Rn and Rm are not changed.

Operation

void CMPGT (int m, int n)
{
  if ((long)R[n] > (long)R[m])
    T = 1;
  else
    T = 0;

  PC += 2;
}

Description
Compares general register Rn and sets the T bit if Rn is greater 0. The value in Rn for the comparison is interpreted as signed integer. The contents of Rn are not changed.

Operation

void CMPPL (int n)
{
  if ((long)R[n] > 0)
    T = 1;
  else
    T = 0;

  PC += 2;
}

Description
Compares general register Rn and sets the T bit if Rn is greater or equal 0. The value in Rn for the comparison is interpreted as signed integer. The contents of Rn are not changed.

Operation

void CMPPZ (int n)
{
  if ((long)R[n] >= 0)
    T = 1;
  else
    T = 0;

  PC += 2;
}

Description
Compares general registers Rn and Rm, and sets the T bit if any of the 4 bytes in Rn are equal to the corresponding byte in Rm. The contents of Rn and Rm are not changed.

Note
This instruction can be used to speed up some string operations such as finding the string length of a zero terminated string or string matching.

Operation

void CMPSTR (int m, int n)
{
  unsigned long temp;
  long HH, HL, LH, LL;
  temp = R[n] ^ R[m];
  HH = (temp & 0xFF000000) >> 24;
  HL = (temp & 0x00FF0000) >> 16;
  LH = (temp & 0x0000FF00) >> 8;
  LL = temp & 0x000000FF;
  HH = HH && HL && LH && LL;

  if (HH == 0)
    T = 1;
  else
    T = 0;

  PC += 2;
}

Example

cmp/str  r2,r3    ! r2 = "ABCD", r3 = "XYCZ"
bt       target   ! T = 1, so branch is taken.

Description
Determines saturation. Signed data is used with this instruction. The saturation upper-limit value is stored in general register Rn if the contents of Rn exceed the saturation upper-limit value, or the saturation lower-limit value is stored in Rn if the contents of Rn are less than the saturation lower-limit value, and the CS bit is set to 1. The saturation upper-limit value is 0x0000007F (127). The saturation lower-limit value is 0xFFFFFF80 (-128).

Note
The CS bit value does not change if the contents of general register Rn do not exceed the saturation upper-limit value or are not less than the saturation lower-limit value.

Operation

void CLIPSB (int n)
{
  if (R[n] > 0x0000007F)
  {
    R[n] = 0x0000007F;
    CS = 1;
  }
  else if (R[n] < 0xFFFFFF80)
  {
    R[n] = 0xFFFFFF80;
    CS = 1;
  }

  PC += 2;
}

Description
Determines saturation. Signed data is used with this instruction. The saturation upper-limit value is stored in general register Rn if the contents of Rn exceed the saturation upper-limit value, or the saturation lower-limit value is stored in Rn if the contents of Rn are less than the saturation lower-limit value, and the CS bit is set to 1. The saturation upper-limit value is 0x00007FFF (32767). The saturation lower-limit value is 0xFFFF8000 (-32768).

Note
The CS bit value does not change if the contents of general register Rn do not exceed the saturation upper-limit value or are not less than the saturation lower-limit value.

Operation

void CLIPSW (int n)
{
  if (R[n] > 0x00007FFF)
  {
    R[n] = 0x00007FFF;
    CS = 1;
  }
  else if (R[n] < 0xFFFF8000)
  {
    R[n] = 0xFFFF8000;
    CS = 1;
  }

  PC += 2;
}

Description
Determines saturation. Unsigned data is used with this instruction. If the contents of general register Rn exceed the saturation value, the saturation value is stored in Rn and the CS bit is set to 1. The saturation value is 0x000000FF (255).

Note
The CS bit value does not change if the contents of general register Rn do not exceed the saturation upper-limit value.

Operation

void CLIPUB (int n)
{
  if (R[n] > 0x000000FF)
  {
    R[n] = 0x000000FF;
    CS = 1;
  }

  PC += 2;
}

Description
Determines saturation. Unsigned data is used with this instruction. If the contents of general register Rn exceed the saturation value, the saturation value is stored in Rn and the CS bit is set to 1. The saturation value is 0x0000FFFF (65535).

Note
The CS bit value does not change if the contents of general register Rn do not exceed the saturation upper-limit value.

Operation

void CLIPUW (int n)
{
  if (R[n] > 0x0000FFFF)
  {
    R[n] = 0x0000FFFF;
    CS = 1;
  }

  PC += 2;
}

Description
Performs initial settings for signed division. This instruction is followed by a DIV1 instruction that executes 1-digit division, for example, and repeated division steps are executed to find the quotient. See the description of the DIV1 instruction for details.

Note
This instruction can also be used to compare the signs of Rm and Rn. If the signs of Rm and Rn are equal, T will be set to 0. If the signs of Rm and Rn are not equal, T will be set to 1.

Operation

void DIV0S (int m, int n)
{
  if ((R[n] & 0x80000000) == 0)
    Q = 0;
  else
    Q = 1;

  if ((R[m] & 0x80000000) == 0)
    M = 0;
  else
    M = 1;

  T = ! (M == Q);
  PC += 2;
}

Description
Performs initial settings for unsigned division. This instruction is followed by a DIV1 instruction that executes 1-digit division, for example, and repeated division steps are executed to find the quotient. See the description of the DIV1 instruction for details.

Operation

void DIV0U (void)
{
  M = Q = T = 0;
  PC += 2;
}

Description
Performs 1-digit division (1-step division) of the 32-bit contents of general register Rn (dividend) by the contents of Rm (divisor). The quotient is obtained by repeated execution of this instruction alone or in combination with other instructions. The specified registers and the M, Q, and T bits must not be modified during these repeated executions.

In 1-step division, the dividend is shifted 1 bit to the left, the divisor is subtracted from this, and the quotient bit is reflected in the Q bit according to whether the result is positive or negative.

Detection of division by zero or overflow is not provided. Check for division by zero and overflow division before executing the division. A remainder operation is not provided. Find the remainder by finding the product of the divisor and the obtained quotient, and subtracting this value from the dividend:
remainder = dividend - (divisor * quotient)
Initial settings should first be made with the DIV0S or DIV0U instruction. DIV1 is executed once for each bit of the divisor. If a quotient of more than 17 bits is required, place an ROTCL instruction before the DIV1 instruction. See the examples for details of the division sequence.

Operation

void DIV1 (int m, int n)
{
  unsigned long tmp0, tmp2;
  unsigned char old_q, tmp1;

  old_q = Q;
  Q = (0x80000000 & R[n]) != 0;
  tmp2 = R[m];
  R[n] <<= 1;
  R[n] |= (unsigned long)T;

  if (old_q == 0)
  {
    if (M == 0)
    {
      tmp0 = R[n];
      R[n] -= tmp2;
      tmp1 = R[n] > tmp0;

      if (Q == 0)
        Q = tmp1;
      else if (Q == 1)
        Q = tmp1 == 0;
    }

    else if (M == 1)
    {
      tmp0 = R[n];
      R[n] += tmp2;
      tmp1 = R[n] < tmp0;

      if (Q == 0)
        Q = tmp1 == 0;
      else if (Q == 1)
        Q = tmp1;
    }
  }

  else if (old_q == 1)
  {
    if (M == 0)
    {
      tmp0 = R[n];
      R[n] += tmp2;
      tmp1 = R[n] < tmp0;

      if (Q == 0)
        Q = tmp1;
      else if (Q == 1)
        Q = tmp1 == 0;
    }

    else if (M == 1)
    {
       tmp0 = R[n];
       R[n] -= tmp2;
       tmp1 = R[n] > tmp0;

       if (Q == 0)
         Q = tmp1 == 0;
       else if (Q == 1)
         Q = tmp1;
    }
  }

  T = (Q == M);
  PC += 2;
}

Example

! r1 (32 bits) / r0 (16 bits) = r1 (16 bits)  (unsigned)

shll16  r0        ! Set divisor in upper 16 bits, clear lower 16 bits to 0

tst     r0,r0     ! Check for division by zero
bt      zero_div

cmp/hs  r0,r1     ! Check for overflow
bt      over_div

div0u             ! Flag initialization

.rept 16 
div1    r0,r1     ! Repeat 16 times
.endr

rotcl   r1 
extu.w  r1,r1     ! r1 = quotient

- - - - - - - - - - - - - - - - 

! r1:r2 (64 bits) / r0 (32 bits) = r2 (32 bits)  (unsigned)

tst     r0,r0     ! Check for division by zero
bt      zero_div

cmp/hs  r0,r1     ! Check for overflow
bt      over_div

div0u             ! Flag initialization

.rept 32
rotcl   r2        ! Repeat 32 times
div1    r0,r1
.endr

rotcl   r2        ! r2 = quotient

- - - - - - - - - - - - - - - - 

! r1 (16 bits) / r0 (16 bits) = r1 (16 bits)  (signed)

shll16  r0        ! Set divisor in upper 16 bits, clear lower 16 bits to 0
exts.w  r1,r1     ! Dividend sign-extended to 32 bits
mov     #0,r2
mov     r1,r3 
rotcl   r3 
subc    r2,r1     ! If dividend is negative, subtract 1
div0s   r0,r1     ! Flag initialization

.rept 16
div1    r0,r1     ! Repeat 16 times
.endr

exts.w  r1,r1 
rotcl   r1        ! r1 = quotient (one's complement notation)
addc    r2,r1     ! If MSB of quotient is 1, add 1 to convert to two's complement notation
exts.w  r1,r1     ! r1 = quotient (two's complement notation)

- - - - - - - - - - - - - - - - 

! r2 (32 bits) / r0 (32 bits) = r2 (32 bits)  (signed)

mov     r2,r3 
rotcl   r3 
subc    r1,r1     ! Dividend sign-extended to 64 bits (r1:r2)
mov     #0,r3
subc    r3,r2     ! If dividend is negative, subtract 1 to convert to one's complement notation
div0s   r0,r1     ! Flag initialization

.rept 32
rotcl   r2        ! Repeat 32 times
div1    r0,r1
.endr

rotcl   r2        ! r2 = quotient (one's complement notation)
addc    r3,r2     ! If MSB of quotient is 1, add 1 to convert to two's complement notation
                  ! r2 = quotient (two's complement notation)

- - - - - - - - - - - - - - - - 
! r4 (8 bits) / r5 (8 bits) = r0 (8 bits)  (unsigned)

extu.b  r4,r4     ! Optional, not needed if value is known to be zero extended.
extu.b  r5,r5     ! Optional, not needed if value is known to be zero extended.
shll8   r5
div0u

.rept 8
div1    r5,r4     ! Repeat 8 times
.endr

rotcl   r4
extu.b  r4,r0

Description
Executes division of the 32-bit contents of a general register Rn (dividend) by the contents of R0 (divisor). This instruction executes signed division and finds the quotient only. A remainder operation is not provided. To obtain the remainder, find the product of the divisor and the obtained quotient, and subtract this value from the dividend. The sign of the remainder will be the same as that of the dividend.

Note
An overflow exception will occur if the negative maximum value (0x00000000) is divided by -1. If division by zero is performed a division by zero exception will occur.

If an interrupt is generated while this instruction is being executed, execution will be halted. The return address will be the start address of this instruction, and this instruction will be re-executed. This avoids increased interrupt latency.

Operation

void DIVS (int n)
{
  R[n] = R[n] / R[0];
  PC += 2;
}

Possible Exceptions

Overflow exception

Division by zero exception

Description
Executes division of the 32-bit contents of a general register Rn (dividend) by the contents of R0 (divisor). This instruction executes unsigned division and finds the quotient only. A remainder operation is not provided. To obtain the remainder, find the product of the divisor and the obtained quotient, and subtract this value from the dividend.

Note
A division by zero exception will occur if division by zero is performed.

If an interrupt is generated while this instruction is being executed, execution will be halted. The return address will be the start address of this instruction, and this instruction will be re-executed. This avoids increased interrupt latency.

Operation

void DIVU (int n)
{
  R[n]= (unsigned long)R[n] / (unsigned long)R[0];
  PC += 2;
}

Possible Exceptions

Division by zero exception

Description
Performs 32-bit multiplication of the contents of general register Rn by the contents of Rm, and stores the 64-bit result in the MACH and MACL registers. The multiplication is performed as a signed arithmetic operation.

Note
On SH4, when MAC*/MUL* is followed by an STS.L MAC*,@-Rn instruction, the latency of MAC*/MUL* is 5 cycles.

Operation

void DMULS (int m, int n)
{
  unsigned long RnL, RnH, RmL, RmH, Res0, Res1, Res2;
  unsigned long temp0, temp1, temp2, temp3;
  long tempm, tempn, fnLmL;

  tempn = (long)R[n];
  tempm = (long)R[m];

  if (tempn < 0)
    tempn = 0 - tempn;

  if (tempm < 0)
    tempm = 0 - tempm;

  if ((long)(R[n] ^ R[m]) < 0)
    fnLmL = -1;
  else
    fnLmL = 0;

  temp1 = (unsigned long)tempn;
  temp2 = (unsigned long)tempm;

  RnL = temp1 & 0x0000FFFF;
  RnH = (temp1 >> 16) & 0x0000FFFF;

  RmL = temp2 & 0x0000FFFF;
  RmH = (temp2 >> 16) & 0x0000FFFF;

  temp0 = RmL * RnL;
  temp1 = RmH * RnL;
  temp2 = RmL * RnH;
  temp3 = RmH * RnH;

  Res2 = 0;
  Res1 = temp1 + temp2;
  if (Res1 < temp1)
    Res2 += 0x00010000;

  temp1 = (Res1 << 16) & 0xFFFF0000;
  Res0 = temp0 + temp1;
  if (Res0 < temp0)
    Res2++;

  Res2 = Res2 + ((Res1 >> 16) & 0x0000FFFF) + temp3;

  if (fnLmL < 0)
  {
    Res2 = ~Res2;
    if (Res0 == 0)
      Res2++;
    else
      Res0 = (~Res0) + 1;
  }

  MACH = Res2;
  MACL = Res0;
  PC += 2;
}

Description
Performs 32-bit multiplication of the contents of general register Rn by the contents of Rm, and stores the 64-bit result in the MACH and MACL registers. The multiplication is performed as an unsigned arithmetic operation.

Note
On SH4, when MAC*/MUL* is followed by an STS.L MAC*,@-Rn instruction, the latency of MAC*/MUL* is 5 cycles.

Operation

void DMULU (int m, int n)
{
  unsigned long RnL, RnH, RmL, RmH, Res0, Res1, Res2;
  unsigned long temp0, temp1, temp2, temp3;

  RnL = R[n] & 0x0000FFFF;
  RnH = (R[n] >> 16) & 0x0000FFFF;

  RmL = R[m] & 0x0000FFFF;
  RmH = (R[m] >> 16) & 0x0000FFFF;

  temp0 = RmL * RnL;
  temp1 = RmH * RnL;
  temp2 = RmL * RnH;
  temp3 = RmH * RnH;

  Res2 = 0
  Res1 = temp1 + temp2;
  if (Res1 < temp1)
    Res2 += 0x00010000;

  temp1 = (Res1 << 16) & 0xFFFF0000;
  Res0 = temp0 + temp1;
  if (Res0 < temp0)
    Res2++;

  Res2 = Res2 + ((Res1 >> 16) & 0x0000FFFF) + temp3;

  MACH = Res2;
  MACL = Res0;
  PC += 2;
}

Description
Decrements the contents of general register Rn by 1 and compares the result with zero. If the result is zero, the T bit is set to 1. If the result is nonzero, the T bit is cleared to 0.

Operation

void DT (int n)
{
  R[n]--;

  if (R[n] == 0)
    T = 1;
  else T = 0;

  PC += 2;
}

Example

    mov   #4,r4      ! Set loop count
loop:
    add   r0,r1
    dt    r5         ! Decrement r5 value and check for 0.
    bf    loop       ! if T = 0 branch to loop
                     ! (in this example, 4 loop iterations are executed)

Description
Sign-extends the contents of general register Rm and stores the result in Rn. The value of Rm bit 7 is transferred to Rn bits 8 to 31.

Operation

void EXTSB (int m, int n)
{
  R[n] = R[m];

  if ((R[m] & 0x00000080) == 0)
    R[n] & = 0x000000FF;
  else
    R[n] |= 0xFFFFFF00;

  PC += 2;
}

Description
Sign-extends the contents of general register Rm and stores the result in Rn. The value of Rm bit 15 is transferred to Rn bits 16 to 31.

Operation

void EXTSW (int m, int n)
{
  R[n] = R[m];

  if ((R[m] & 0x00008000) == 0)
    R[n] & = 0x0000FFFF;
  else
    R[n] |= 0xFFFF0000;

  PC += 2;
}

Description
Zero-extends the contents of general register Rm and stores the result in Rn. 0 is transferred to Rn bits 8 to 31.

Operation

void EXTUB (int m, int n)
{
  R[n] = R[m];
  R[n] &= 0x000000FF;
  PC += 2;
}

Description
Zero-extends the contents of general register Rm and stores the result in Rn. 0 is transferred to Rn bits 16 to 31.

Operation

void EXTUW (int m, int n)
{
  R[n] = R[m];
  R[n] &= 0x0000FFFF;
  PC += 2;
}

Description
Performs signed multiplication of the 32-bit operands whose addresses are the contents of general registers Rm and Rn, adds the 64-bit result to the MAC register contents, and stores the result in the MAC register. Operands Rm and Rn are each incremented by 4 each time they are read.

When the S bit is cleared to 0, the 64-bit result is stored in the coupled MACH and MACL registers.

When bit S is set to 1, addition to the MAC register is a saturation operation of 48 bits starting from the LSB. For the saturation operation, only the lower 48 bits of the MACL register are enabled and the result is limited to a range of 0xFFFF800000000000 (minimum) and 0x00007FFFFFFFFFFF (maximum).

Note
On SH4, when MAC*/MUL* is followed by an STS.L MAC*,@-Rn instruction, the latency of MAC*/MUL* is 5 cycles. In the case of consecutive executions of MAC.W/MAC.L, the latency is decreased to 2 cycles.

Operation

void MACL (int m, int n)
{
  unsigned long RnL, RnH, RmL, RmH, Res0, Res1, Res2;
  unsigned long temp0, temp1, temp2, temp3;
  long tempm, tempn, fnLmL;

  tempn = Read_32 (R[n]);
  R[n] += 4;
  tempm = Read_32 (R[m]);
  R[m] += 4;

  if ((long)(tempn ^ tempm) < 0)
    fnLmL = -1;
  else
    fnLmL = 0;

  if (tempn < 0)
    tempn = 0 - tempn;
  if (tempm < 0)
    tempm = 0 - tempm;

  temp1 = (unsigned long)tempn;
  temp2 = (unsigned long)tempm;

  RnL = temp1 & 0x0000FFFF;
  RnH = (temp1 >> 16) & 0x0000FFFF;
  RmL = temp2 & 0x0000FFFF;
  RmH = (temp2 >> 16) & 0x0000FFFF;
  temp0 = RmL * RnL;
  temp1 = RmH * RnL;
  temp2 = RmL * RnH;
  temp3 = RmH * RnH;

  Res2 = 0;

  Res1 = temp1 + temp2;
  if (Res1 < temp1)
    Res2 += 0x00010000;

  temp1 = (Res1 << 16) & 0xFFFF0000;

  Res0 = temp0 + temp1;
  if (Res0 < temp0)
    Res2++;

  Res2 = Res2 + ((Res1 >> 16) & 0x0000FFFF) + temp3;

  if(fnLmL < 0)
  {
    Res2 = ~Res2;
    if (Res0 == 0)
      Res2++;
    else
      Res0 = (~Res0) + 1;
  }

  if (S == 1)
  {
    Res0 = MACL + Res0;
    if (MACL > Res0)
      Res2++;

    Res2 += MACH & 0x0000FFFF;

    if (((long)Res2 < 0) && (Res2 < 0xFFFF8000))
    {
      Res2 = 0xFFFF8000;
      Res0 = 0x00000000;
    }

    if (((long)Res2 > 0) && (Res2 > 0x00007FFF))
    {
      Res2 = 0x00007FFF;
      Res0 = 0xFFFFFFFF;
    }

    MACH = (Res2 & 0x0000FFFF) | (MACH & 0xFFFF0000);
    MACL = Res0;
  }
  else
  {
    Res0 = MACL + Res0;
    if (MACL > Res0)
      Res2 ++;

    Res2 += MACH;
    MACH = Res2;
    MACL = Res0;
  }

  PC += 2;
}

Possible Exceptions

Data TLB multiple-hit exception

Data TLB miss exception

Data TLB protection violation exception

Data address error

Description
Performs signed multiplication of the 16-bit operands whose addresses are the contents of general registers Rm and Rn, adds the 32-bit result to the MAC register contents, and stores the result in the MAC register. Operands Rm and Rn are each incremented by 2 each time they are read.

If the S bit is 0, a 16 * 16 + 64 -> 64-bit multiply-and-accumulate operation is performed, and the 64-bit result is stored in the linked MACH and MACL registers.

If the S bit is 1, a 16 * 16 + 32 -> 32-bit multiply-and-accumulate operation is performed, and the addition to the MAC register contents is a saturation operation. In a saturation operation, only the MACL register is valid, and the result range is limited to 0x80000000 (minimum value) to 0x7FFFFFFF (maximum value). If overflow occurs, the LSB of the MACH register is set to 1. 0x80000000 (minimum value) is stored in the MACL register if the result overflows in the negative direction, and 0x7FFFFFFF (maximum value) is stored if the result overflows in the positive direction

Note
When the S bit is 0, the SH2 and SH-DSP CPU perform a 16 * 16 + 64 -> 64 bit multiply and accumulate operation and the SH1 CPU performs a 16 * 16 + 42 -> 42 bit multiply and accumulate operation.

On SH4, when MAC*/MUL* is followed by an STS.L MAC*,@-Rn instruction, the latency of MAC*/MUL* is 5 cycles. In the case of consecutive executions of MAC.W/MAC.L, the latency is decreased to 2 cycles.

Operation

void MACW (int m, int n)
{
  long tempm, tempn, dest, src, ans;
  unsigned long templ;

  tempn = Read_16 (R[n]);
  R[n] += 2;
  tempm = Read_16 (R[m]);
  R[m] += 2;

  templ = MACL;
  tempm = ((long)(short)tempn * (long)(short)tempm);

  if ((long)MACL >= 0)
    dest = 0;
  else
    dest = 1;

  if ((long)tempm >= 0)
  {
    src = 0;
    tempn = 0;
  }
  else
  {
    src = 1;
    tempn = 0xFFFFFFFF;
  }

  src += dest;
  MACL += tempm;

  if ((long)MACL >= 0)
    ans = 0;
  else
    ans = 1;

  ans += dest;

  if (S == 1)
  {
    if (ans == 1)
    {
      #if SH1
      if (src == 0 || src == 2)
        MACH |= 0x00000001;
      #endif

      if (src == 0)
        MACL = 0x7FFFFFFF;
      if (src == 2)
        MACL = 0x80000000;
    }
  }
  else
  {
    MACH += tempn;
    if (templ > MACL)
      MACH += 1;

    #if SH1
    if ((MACH & 0x00000200) == 0)
      MACH &= 0x000003FF;
    else
      MACH |= 0xFFFFFC00;
    #endif
  }

  PC += 2;
}

Possible Exceptions

Data TLB multiple-hit exception

Data TLB miss exception

Data TLB protection violation exception

Data address error

Description
Performs 32-bit multiplication of the contents of general registers Rn and Rm, and stores the lower 32 bits of the result in the MACL register. The contents of MACH are not changed.

Note
On SH4, when MAC*/MUL* is followed by an STS.L MAC*,@-Rn instruction, the latency of MAC*/MUL* is 5 cycles.

Operation

void MULL (int m, int n)
{
  MACL = R[n] * R[m];
  PC += 2;
}

Description
Performs 32-bit multiplication of the contents of general register R0 by Rn, and stores the lower 32 bits of the result in general register Rn.

Operation

void MULR (int n)
{
  R[n] = R[0] * R[n];
  PC += 2;
}

Description
Performs 16-bit multiplication of the contents of general registers Rn and Rm, and stores the 32-bit result in the MACL register. The multiplication is performed as a signed arithmetic operation. The contents of MACH are not changed.

Note
On SH4, when MAC*/MUL* is followed by an STS.L MAC*,@-Rn instruction, the latency of MAC*/MUL* is 5 cycles.

Operation

void MULS (int m, int n)
{
  MACL = ((long)(short)R[n] * (long)(short)R[m]);
  PC += 2;
}

Description
Performs 16-bit multiplication of the contents of general registers Rn and Rm, and stores the 32-bit result in the MACL register. The multiplication is performed as an unsigned arithmetic operation. The contents of MACH are not changed.

Note
On SH4, when MAC*/MUL* is followed by an STS.L MAC*,@-Rn instruction, the latency of MAC*/MUL* is 5 cycles.

Operation

void MULU (int m, int n)
{
  MACL = ((unsigned long)(unsigned short)R[n]* (unsigned long)(unsigned short)R[m];
  PC += 2;
}

Description
Finds the two's complement of the contents of general register Rm and stores the result in Rn. That is, it subtracts Rm from 0 and stores the result in Rn.

Operation

void NEG (int m, int n)
{
  R[n] = 0 - R[m];
  PC += 2;
}

Description
Subtracts the contents of general register Rm and the T bit from 0 and stores the result in Rn. A borrow resulting from the operation is reflected in the T bit. This instruction can be used for sign inversion of a value exceeding 32 bits.

Note
This instruction can also be used to efficiently store the reversed T bit value in a general register, if the MOVRT instruction is not available.

Operation

void NEGC (int m, int n)
{
  unsigned long temp;
  temp = 0 - R[m];
  R[n] = temp - T;

  if (0 < temp)
    T = 1;
  else
    T = 0;

  if (temp < R[n])
    T = 1;

  PC += 2;
}

Example

! Sign inversion of r0:r1 (64 bits)

clrt
negc   r1,r1    ! Before execution: r1 = 0x00000001, T = 0
                ! After execution: r1 = 0xFFFFFFFF, T = 1
negc   r0,r0    ! Before execution: r0 = 0x00000000, T = 1
                ! After execution: r0 = 0xFFFFFFFF, T = 1

- - - - - - - - - - - - - - - - 

! Store reversed T bit in r0

mov    #-1,r1
negc   r1,r0    ! r0 = 0 - (-1) - T
                ! r0 = 1 - T
                ! Notice that T bit will be modified by the negc operation.
                ! In this case, T will be always set to 1.

Description
Subtracts the contents of general register Rm from the contents of general register Rn and stores the result in Rn. For immediate data subtraction, ADD #imm,Rn should be used.

Operation

void SUB (int m, int n)
{
  R[n] -= R[m];
  PC += 2;
}

Description
Subtracts the contents of general register Rm and the T bit from the contents of general register Rn, and stores the result in Rn. A borrow resulting from the operation is reflected in the T bit. This instruction is used for subtractions exceeding 32 bits.

Note
This instruction can also be used to store the T bit to all the bits of a general register.

Operation

void SUBC (int m, int n)
{
  unsigned long tmp0, tmp1;
  tmp1 = R[n] - R[m];
  tmp0 = R[n];
  R[n] = tmp1 - T;

  if (tmp0 < tmp1)
    T = 1;
  else
    T = 0;

  if (tmp1 < R[n])
    T = 1;

  PC += 2;
}

Example

! r0:r1(64 bits) - r2:r3(64 bits) = r0:r1(64 bits)

clrt
subc   r3,r1    ! Before execution: T = 0, r1 = 0x00000000, r3 = 0x00000001
                ! After execution: T = 1, r1 = 0xFFFFFFFF
subc   r2,r0    ! Before execution: T = 1, r0 = 0x00000000, r2 = 0x00000000
                ! After execution: T = 1, r0 = 0xFFFFFFFF

- - - - - - - - - - - - - - - - 

! Store T bit to all bits of r0

subc   r0,r0    ! r0 = r0 - r0 - T
                ! r0 = 0 - T
                ! Notice that the T bit is modified by the subc operation.

Description
Subtracts the contents of general register Rm from the contents of general register Rn, and stores the result in Rn. If underflow occurs, the T bit is set.

Operation

void SUBV (int m, int n)
{
  long dest, src, ans;

  if ((long)R[n] >= 0)
    dest = 0;
  else
    dest = 1;

  if ((long)R[m] >= 0)
    src = 0;
  else
    src = 1;

  src += dest;
  R[n] -= R[m];

  if ((long)R[n] >= 0)
    ans = 0;
  else
    ans = 1;

  ans += dest;

  if (src == 1)
  {
    if (ans == 1)
      T = 1;
    else
      T = 0;
  }
  else
    T = 0;

  PC += 2;
}

Example

subv   r0,r1    ! Before execution: r0 = 0x00000002, r1 = 0x80000001
                ! After execution: r1 = 0x7FFFFFFF, T = 1

subv   r2,r3    ! Before execution: r2 = 0xFFFFFFFE, r3 = 0x7FFFFFFE
                ! After execution r3 = 0x80000000, T = 1

Description
ANDs the contents of general registers Rn and Rm and stores the result in Rn.

Operation

void AND (int m, int n)
{
  R[n] &= R[m];
  PC += 2;
}

Description
ANDs the contents of general register R0 and the zero-extended immediate value and stores the result in R0.

Note
Since the 8-bit immediate value is zero-extended, the upper 24 bits of R0 are always cleared to zero.

Operation

void ANDI (int i)
{
  R[0] &= (0x000000FF & (long)i);
  PC += 2;
}

Description
ANDs the contents of the memory byte indicated by the indirect GBR address with the immediate value and writes the result back to the memory byte.

Operation

void ANDM (long i)
{
  long temp = Read_8 (GBR + R[0]);
  temp &= 0x000000FF & (long)i;
  Write_8 (GBR + R[0], temp);
  PC += 2;
}

Possible Exceptions

Data TLB multiple-hit exception

Data TLB miss exception

Data TLB protection violation exception

Initial page write exception

Data address error

Exceptions are checked taking a data access by this instruction as a byte load and a byte store.

Description
Finds the one's complement of the contents of general register Rm and stores the result in Rn. That is, it inverts the Rm bits and stores the result in Rn.

Operation

void NOT (int m, int n)
{
  R[n] = ~R[m];
  PC += 2;
}

Description
ORs the contents of general registers Rn and Rm and stores the result in Rn.

Operation

void OR (int m, int n)
{
  R[n] |= R[m];
  PC += 2;
}

Description
ORs the contents of general register R0 and the zero-extended immediate value and stores the result in R0.

Note
Since the 8-bit immediate value is zero-extended, the upper 24 bits of R0 are not modified.

Operation

void ORI (int i)
{
  R[0] |= (0x000000FF & (long)i);
  PC += 2;
}

Description
ORs the contents of the memory byte indicated by the indirect GBR address with the immediate value and writes the result back to the memory byte.

Operation

void ORM (int i)
{
  long temp = Read_8 (GBR + R[0]);
  temp |= (0x000000FF & (long)i);
  Write_8 (GBR + R[0], temp);
  PC += 2;
}

Possible Exceptions

Data TLB multiple-hit exception

Data TLB miss exception

Data TLB protection violation exception

Initial page write exception

Data address error

Exceptions are checked taking a data access by this instruction as a byte load and a byte store.

Description
Reads byte data from the address specified by general register Rn, and sets the T bit to 1 if the data is 0, or clears the T bit to 0 if the data is not 0. Then, data bit 7 is set to 1, and the data is written to the address specified by Rn. During this operation, the bus is not released.

On SH4 and SH4A this instruction purges the cache block corresponding to the memory area specified by the contents of general register Rn. The purge operation is executed as follows.
In a purge operation, data is accessed using the contents of general register Rn as the effective address. If there is a cache hit and the corresponding cache block is dirty (U bit = 1), the contents of that cache block are written back to external memory, and the cache block is then invalidated (by clearing the V bit to 0). If there is a cache hit and the corresponding cache block is clean (U bit = 0), the cache block is simply invalidated (by clearing the V bit to 0). A purge is not executed in the event of a cache miss, or if the accessed memory location is non-cacheable.

Note
The two TAS.B memory accesses are executed automatically. Another memory access is not executed between the two TAS.B accesses.

On SH3 the destination of the TAS instruction should be placed in a non-cacheable space when the cache is enabled.

Operation

void TAS (int n)
{
  int temp = Read_8 (R[n]); // Bus Lock

  if (temp == 0)
    T = 1;
  else
    T = 0;

  temp |= 0x00000080;
  Write_8 (R[n], temp);  // Bus unlock
  PC += 2;
}

Possible Exceptions

Data TLB multiple-hit exception

Data TLB miss exception

Data TLB protection violation exception

Initial page write exception

Data address error

Exceptions are checked taking a data access by this instruction as a byte load and a byte store.

Description
ANDs the contents of general registers Rn and Rm, and sets the T bit if the result is zero. If the result is nonzero, the T bit is cleared. The contents of Rn are not changed.

Operation

void TST (int m, int n)
{
  if ((R[n] & R[m]) == 0)
    T = 1;
  else
    T = 0;

  PC += 2;
}

Description
ANDs the contents of general register R0 and the zero-extended immediate value and sets the T bit if the result is zero. If the result is nonzero, the T bit is cleared. The contents of Rn are not changed.

Note
Since the 8-bit immediate value is zero-extended, this instruction can only be used to test the lower 8 bits of R0.

Operation

void TSTI (int i)
{
  long temp = R[0] & (0x000000FF & (long)i);

  if (temp == 0)
    T = 1;
  else
    T = 0;

  PC += 2;
}

Description
ANDs the contents of the memory byte indicated by the indirect GBR address with the zero-extended immediate value and sets the T bit if the result is zero. If the result is nonzero, the T bit is cleared. The contents of the memory byte are not changed.

Operation

void TSTM (int i)
{
  long temp = Read_8 (GBR + R[0]);
  temp &= (0x000000FF & (long)i);

  if (temp == 0)
    T = 1;
  else
    T = 0;

  PC += 2;
}

Possible Exceptions

Data TLB multiple-hit exception

Data TLB miss exception

Data TLB protection violation exception

Data address error

Exceptions are checked taking a data access by this instruction as a byte load and a byte store.

Description
XORs the contents of general registers Rn and Rm and stores the result in Rn.

Operation

void XOR (long m, long n)
{
  R[n] ^= R[m];
  PC += 2;
}

Description
XORs the contents of general register R0 and the zero-extended immediate value and stores the result in R0.

Note
Since the 8-bit immediate value is zero-extended, the upper 24 bits of R0 are not modified.

Operation

void XORI (int i)
{
  R[0] ^= (0x000000FF & (long)i);
  PC += 2;
}

Description
XORs the contents of the memory byte indicated by the indirect GBR address with the immediate value and writes the result back to the memory byte.

Operation

void XORM (int i)
{
  int temp = Read_8 (GBR + R[0]);
  temp ^= (0x000000FF & (long)i);
  Write_8 (GBR + R[0], temp);
  PC += 2;
}

Possible Exceptions

Data TLB multiple-hit exception

Data TLB miss exception

Data TLB protection violation exception

Initial page write exception

Data address error

Exceptions are checked taking a data access by this instruction as a byte load and a byte store.

Description
Rotates the contents of general register Rn one bit to the left through the T bit, and stores the result in Rn. The bit rotated out of the operand is transferred to the T bit.


Operation

void ROTCL (int n)
{
  long temp;

  if ((R[n] & 0x80000000) == 0)
    temp = 0;
  else
    temp = 1;

  R[n] <<= 1;

  if (T == 1)
    R[n] |= 0x00000001;
  else
    R[n] &= 0xFFFFFFFE;

  if (temp == 1)
    T = 1;
  else
    T = 0;

  PC += 2;
}

Description
Rotates the contents of general register Rn one bit to the right through the T bit, and stores the result in Rn. The bit rotated out of the operand is transferred to the T bit.


Operation

void ROTCR (int n)
{
  long temp;

  if ((R[n] & 0x00000001) == 0)
    temp = 0;
  else
    temp = 1;

  R[n] >>= 1;

  if (T == 1)
    R[n] |= 0x80000000;
  else
    R[n] &= 0x7FFFFFFF;

  if (temp == 1)
    T = 1;
  else
    T = 0;

  PC += 2;
}

Description
Rotates the contents of general register Rn one bit to the left, and stores the result in Rn. The bit rotated out of the operand is transferred to the T bit.


Operation

void ROTL (int n)
{
  if ((R[n] & 0x80000000) == 0)
    T = 0;
  else
    T = 1;

  R[n] <<= 1;

  if (T == 1)
    R[n] |= 0x00000001;
  else
    R[n] &= 0xFFFFFFFE;

  PC += 2;
}

Description
Rotates the contents of general register Rn one bit to the right, and stores the result in Rn. The bit rotated out of the operand is transferred to the T bit.


Operation

void ROTR (int n)
{
  if ((R[n] & 0x00000001) == 0)
    T = 0;
  else
    T = 1;

  R[n] >>= 1;

  if (T == 1)
    R[n] |= 0x80000000;
  else
    R[n] &= 0x7FFFFFFF;

  PC += 2;
}

Description
Arithmetically shifts the contents of general register Rn. General register Rm specifies the shift direction and the number of bits to be shifted.

Rn register contents are shifted to the left if the Rm register value is positive, and to the right if negative. In a shift to the right, the MSB is added at the upper end.

The number of bits to be shifted is specified by the lower 5 bits (bits 4 to 0) of the Rm register. If the value is negative (MSB = 1), the Rm register is represented as a two's complement. The left shift range is 0 to 31, and the right shift range, 1 to 32.


Note
On SH4, if there is a load of the shift amount immediately before an SHAD/SHLD instruction, the latency of the load is increased by 1 cycle.

Operation

void SHAD (int m, int n)
{
  int sgn = R[m] & 0x80000000;

  if (sgn == 0)
    R[n] <<= (R[m] & 0x1F);
  else if ((R[m] & 0x1F) == 0)
  {
    if ((R[n] & 0x80000000) == 0)
      R[n] = 0;
    else
      R[n] = 0xFFFFFFFF;
  }
  else
    R[n] = (long)R[n] >> ((~R[m] & 0x1F) + 1);

  PC += 2;
}

Description
Arithmetically shifts the contents of general register Rn one bit to the left and stores the result in Rn. The bit shifted out of the operand is transferred to the T bit.


Operation

void SHAL (int n)
{
  if ((R[n] & 0x80000000) == 0)
    T = 0;
  else
    T = 1;

  R[n] <<= 1;
  PC += 2;
}

Description
Arithmetically shifts the contents of general register Rn one bit to the right and stores the result in Rn. The bit shifted out of the operand is transferred to the T bit.


Operation

void SHAR (int n)
{
  long temp;

  if ((R[n] & 0x00000001) == 0)
    T = 0;
  else
    T = 1;

  if ((R[n] & 0x80000000) == 0)
    temp = 0;
  else
    temp = 1;

  R[n] >>= 1;

  if (temp == 1)
    R[n] |= 0x80000000;
  else
    R[n] &= 0x7FFFFFFF;

  PC += 2;
}

Description
Logically shifts the contents of general register Rn. General register Rm specifies the shift direction and the number of bits to be shifted.

Rn register contents are shifted to the left if the Rm register value is positive, and to the right if negative. In a shift to the right, 0s are added at the upper end.

The number of bits to be shifted is specified by the lower 5 bits (bits 4 to 0) of the Rm register. If the value is negative (MSB = 1), the Rm register is represented as a two's complement. The left shift range is 0 to 31, and the right shift range, 1 to 32.


Note
On SH4, if there is a load of the shift amount immediately before an SHAD/SHLD instruction, the latency of the load is increased by 1 cycle.

Operation

void SHLD (int m, int n)
{
  int sgn = R[m] & 0x80000000;

  if (sgn == 0)
    R[n] <<= (R[m] & 0x1F);
  else if ((R[m] & 0x1F) == 0)
    R[n] = 0;
  else
    R[n] = (unsigned)R[n] >> ((~R[m] & 0x1F) + 1);

  PC += 2;
}

Description
Logically shifts the contents of general register Rn one bit to the left and stores the result in Rn. The bit shifted out of the operand is transferred to the T bit.


Note
Effectively, the operation performed is the same as the SHAL instruction.

Operation

void SHLL (int n)
{
  if ((R[n] & 0x80000000) == 0)
    T = 0;
  else
    T = 1;

  R[n] <<= 1;
  PC += 2;
}

Description
Logically shifts the contents of general register Rn 2 bits to the left and stores the result in Rn. The bits shifted out of the operand are discarded.


Operation

void SHLL2 (int n)
{
  R[n] <<= 2;
  PC += 2;
}

Description
Logically shifts the contents of general register Rn 8 bits to the left and stores the result in Rn. The bits shifted out of the operand are discarded.


Operation

void SHLL8 (int n)
{
  R[n] <<= 8;
  PC += 2;
}

Description
Logically shifts the contents of general register Rn 16 bits to the left and stores the result in Rn. The bits shifted out of the operand are discarded.


Operation

void SHLL16 (int n)
{
  R[n] <<= 16;
  PC += 2;
}

Description
Logically shifts the contents of general register Rn one bit to the right and stores the result in Rn. The bit shifted out of the operand is transferred to the T bit.


Operation

void SHLR (int n)
{
  if ((R[n] & 0x00000001) == 0)
    T = 0;
  else
    T = 1;

  R[n] >>= 1;
  R[n] &= 0x7FFFFFFF;
  PC += 2;
}

Description
Logically shifts the contents of general register Rn 2 bits to the right, and stores the result in Rn. The bits shifted out of the operand are discarded.


Operation

void SHLR2 (int n)
{
  R[n] >>= 2;
  R[n] &= 0x3FFFFFFF;
  PC += 2;
}

Description
Logically shifts the contents of general register Rn 8 bits to the right, and stores the result in Rn. The bits shifted out of the operand are discarded.


Operation

void SHLR8 (int n)
{
  R[n] >>= 8;
  R[n] &= 0x00FFFFFF;
  PC += 2;
}

Description
Logically shifts the contents of general register Rn 16 bits to the right and stores the result in Rn. The bits shifted out of the operand are discarded.


Operation

void SHLR16 (int n)
{
  R[n] >>= 16;
  R[n] &= 0x0000FFFF;
  PC += 2;
}

Description
This is a conditional branch instruction that references the T bit. The branch is taken if T = 0, and not taken if T = 1. The branch destination is address (PC + 4 + displacement * 2). The PC source value is the BF instruction address. As the 8-bit displacement is multiplied by two after sign-extension, the branch destination can be located in the range from -256 to +254 bytes from the BF instruction.

Note
If the branch destination cannot be reached, the branch must be handled by using BF in combination with a BRA or JMP instruction, for example.

On some SH4 implementations a branch with a displacement value of zero does not cause the pipeline I-stage to be stalled even if the branch is taken. This can be utilized for efficient conditional operations.

On some SH2E implementations (SH7055) there is an FPU related hardware bug which affects this instruction. The recommended workaround is to use bt/s with a nop in the delay slot. See also documents "sh2eoc.pdf" and "win_update_a.pdf".

Operation

void BF (int d)
{
  int disp;
  if ((d & 0x80) == 0)
    disp = (0x000000FF & d);
  else
    disp = (0xFFFFFF00 | d);

  if (T == 0)
    PC = PC + 4 + (disp << 1);
  else
    PC += 2;
}

Possible Exceptions

Slot illegal instruction exception

Description
This is a delayed conditional branch instruction that references the T bit. If T = 1, the next instruction is executed and the branch is not taken. If T = 0, the branch is taken after execution of the next instruction.

The branch destination is address (PC + 4 + displacement * 2). The PC source value is the BF/S instruction address. As the 8-bit displacement is multiplied by two after sign-extension, the branch destination can be located in the range from -256 to +254 bytes from the BF/S instruction.

Note
As this is a delayed branch instruction, when the branch condition is satisfied, the instruction following this instruction is executed before the branch destination instruction.

Interrupts are not accepted between this instruction and the following instruction.

If the following instruction is a branch instruction, it is identified as a slot illegal instruction.

If this instruction is located in the delay slot immediately following a delayed branch instruction, it is identified as a slot illegal instruction.

If the branch destination cannot be reached, the branch must be handled by using BF/S in combination with a BRA or JMP instruction, for example.

Operation

void BFS (int d)
{
  int disp;
  unsigned int temp;
  temp = PC;
  if ((d & 0x80) == 0)
    disp = (0x000000FF & d);
  else
    disp = (0xFFFFFF00 | d);

  if (T == 0)
    PC = PC + 4 + (disp << 1);
  else
    PC += 4;

  Delay_Slot (temp + 2);
}

Possible Exceptions

Slot illegal instruction exception

Description
This is a conditional branch instruction that references the T bit. The branch is taken if T = 1, and not taken if T = 0. The branch destination is address (PC + 4 + displacement * 2). The PC source value is the BT instruction address. As the 8-bit displacement is multiplied by two after sign-extension, the branch destination can be located in the range from -256 to +254 bytes from the BT instruction.

Note
If the branch destination cannot be reached, the branch must be handled by using BT in combination with a BRA or JMP instruction, for example.

On some SH4 implementations a branch with a displacement value of zero does not cause the pipeline I-stage to be stalled even if the branch is taken. This can be utilized for efficient conditional operations.

On some SH2E implementations (SH7055) there is an FPU related hardware bug which affects this instruction. The recommended workaround is to use bt/s with a nop in the delay slot. See also documents "sh2eoc.pdf" and "win_update_a.pdf".

Operation

void BT (int d)
{
  int disp;
  if ((d & 0x80) == 0)
    disp = (0x000000FF & d);
  else
    disp = (0xFFFFFF00 | d);

  if (T == 1)
    PC = PC + 4 + (disp << 1);
  else
    PC += 2;
}

Possible Exceptions

Slot illegal instruction exception

Description
This is a conditional branch instruction that references the T bit. The branch is taken if T = 1, and not taken if T = 0. The PC source value is the BT/S instruction address. As the 8-bit displacement is multiplied by two after sign-extension, the branch destination can be located in the range from -256 to +254 bytes from the BT/S instruction.

Note
As this is a delayed branch instruction, when the branch condition is satisfied, the instruction following this instruction is executed before the branch destination instruction.

Interrupts are not accepted between this instruction and the following instruction.

If the following instruction is a branch instruction, it is identified as a slot illegal instruction.

If the branch destination cannot be reached, the branch must be handled by using BT/S in combination with a BRA or JMP instruction, for example.

Operation

void BTS (int d)
{
  int disp;
  unsigned temp;
  temp = PC;

  if ((d & 0x80) == 0)
    disp = (0x000000FF & d);
  else
    disp = (0xFFFFFF00 | d);

  if (T == 1)
    PC = PC + 4 + (disp << 1);
  else
    PC += 4;

  Delay_Slot (temp + 2);
}

Possible Exceptions

Slot illegal instruction exception

Description
This is an unconditional branch instruction. The branch destination is address (PC + 4 + displacement * 2). The PC source value is the BRA instruction address. As the 12-bit displacement is multiplied by two after sign-extension, the branch destination can be located in the range from -4096 to +4094 bytes from the BRA instruction. If the branch destination cannot be reached, this branch can be performed with a JMP instruction.

Note
As this is a delayed branch instruction, the instruction following this instruction is executed before the branch destination instruction.

Interrupts are not accepted between this instruction and the following instruction.

If the following instruction is a branch instruction, it is identified as a slot illegal instruction.

Operation

void BRA (int d)
{
  int disp;
  unsigned int temp;
  temp = PC;

  if ((d & 0x800) == 0)
    disp = (0x00000FFF & d);
  else
    disp = (0xFFFFF000 | d);

  PC = PC + 4 + (disp << 1);
  Delay_Slot(temp + 2);
}

Possible Exceptions

Slot illegal instruction exception

Description
This is an unconditional branch instruction. The branch destination is address (PC + 4 + Rm).

Note
As this is a delayed branch instruction, the instruction following this instruction is executed before the branch destination instruction.

Interrupts are not accepted between this instruction and the following instruction.

If the following instruction is a branch instruction, it is identified as a slot illegal instruction.

Operation

void BRAF (int m)
{
  unsigned int temp;
  temp = PC;
  PC = PC + 4 + R[m];
  Delay_Slot (temp + 2);
}

Possible Exceptions

Slot illegal instruction exception

Description
Branches to address (PC + 4 + displacement * 2), and stores address (PC + 4) in PR. The PC source value is the BSR instruction address. As the 12-bit displacement is multiplied by two after sign-extension, the branch destination can be located in the range from -4096 to +4094 bytes from the BSR instruction. If the branch destination cannot be reached, this branch can be performed with a JSR instruction.

Note
As this is a delayed branch instruction, the instruction following this instruction is executed before the branch destination instruction.

Interrupts are not accepted between this instruction and the following instruction.

If the following instruction is a branch instruction, it is identified as a slot illegal instruction.

Operation

void BSR (int d)
{
  int disp;
  unsigned int temp;
  temp = PC;

  if ((d & 0x800) == 0)
    disp = (0x00000FFF & d);
  else
    disp = (0xFFFFF000 | d);

  PR = PC + 4;
  PC = PC + 4 + (disp << 1);
  Delay_Slot (temp + 2);
}

Possible Exceptions

Slot illegal instruction exception

Description
Branches to address (PC + 4 + Rm), and stores address (PC + 4) in PR. The PC source value is the BSRF instruction address. The branch destination address is the result of adding the 32-bit contents of general register Rm to PC + 4.

Note
As this is a delayed branch instruction, the instruction following this instruction is executed before the branch destination instruction.

Interrupts are not accepted between this instruction and the following instruction.

If the following instruction is a branch instruction, it is identified as a slot illegal instruction.

Operation

void BSRF (int m)
{
  unsigned int temp;
  temp = PC;
  PR = PC + 4;
  PC = PC + 4 + R[m];
  Delay_Slot (temp + 2);
}

Possible Exceptions

Slot illegal instruction exception

Description
Unconditionally makes a delayed branch to the address specified by Rm.

Note
As this is a delayed branch instruction, the instruction following this instruction is executed before the branch destination instruction.

Interrupts are not accepted between this instruction and the following instruction.

If the following instruction is a branch instruction, it is identified as a slot illegal instruction.

Operation

void JMP (int m)
{
  unsigned int temp;
  temp = PC;
  PC = R[m];
  Delay_Slot (temp + 2);
}

Possible Exceptions

Slot illegal instruction exception

Description
Makes a delayed branch to the subroutine procedure at the specified address after execution of the following instruction. Return address (PC + 4) is saved in PR, and a branch is made to the address indicated by general register Rm. JSR is used in combination with RTS for subroutine procedure calls.

Note
As this is a delayed branch instruction, the instruction following this instruction is executed before the branch destination instruction.

Interrupts are not accepted between this instruction and the following instruction.

If the following instruction is a branch instruction, it is identified as a slot illegal instruction.

Operation

void JSR (int m)
{
  unsigned int temp;
  temp = PC;
  PR = PC + 4;
  PC = R[m];
  Delay_Slot (temp + 2);
}

Possible Exceptions

Slot illegal instruction exception

Description
Branches to a subroutine procedure at the designated address. The contents of PC are stored in PR and execution branches to the address indicated by the contents of general register Rm as 32-bit data. The stored contents of PC indicate the starting address of the second instruction after the present instruction. This instruction is used with RTS as a subroutine procedure call.

Note
This is not a delayed branch instruction.

Operation

void JSRN (int m)
{
  unsigned long temp;
  temp = PC;
  PR = PC + 2;
  PC = R[m];
}

Possible Exceptions

Slot illegal instruction exception

Description
Branches to a subroutine procedure at the designated address. The contents of PC are stored in PR and execution branches to the address indicated by the address read from memory address (disp × 4 + TBR). The stored contents of PC indicate the starting address of the second instruction after the present instruction. This instruction is used with RTS as a subroutine procedure call.

Note
This is not a delayed branch instruction.

Operation

void JSRNM (int d)
{
  long disp = (0x000000FF & d);
  PR = PC + 2;
  PC = Read_32 (TBR + (disp << 2));
}

Possible Exceptions

Slot illegal instruction exception

Description
Returns from a subroutine procedure by restoring the PC from PR. Processing continues from the address indicated by the restored PC value. This instruction can be used to return from a subroutine procedure called by a BSR or JSR instruction to the source of the call.

Note
As this is a delayed branch instruction, the instruction following this instruction is executed before the branch destination instruction.

Interrupts are not accepted between this instruction and the following instruction.

If the following instruction is a branch instruction, it is identified as a slot illegal instruction.

The instruction that restores PR must be executed before the RTS instruction. This restore instruction cannot be in the RTS delay slot.

Operation

void RTS (void)
{
  unsigned int temp;
  temp = PC;
  PC = PR;
  Delay_Slot (temp + 2);
}

Possible Exceptions

Slot illegal instruction exception

Description
Performs a return from a subroutine procedure. That is, the PC is restored from PR, and processing is resumed from the address indicated by the PC. This instruction enables a return to be made from a subroutine procedure called by a BSR or JSR instruction to the origin of the call.

Note
This is not a delayed branch instruction.

Operation

void RTSN (void)
{
  PC = PR;
}

Possible Exceptions

Slot illegal instruction exception

Description
Performs a return from a subroutine procedure after a transfer from specified general register Rm to R0. That is, after the Rm value is stored in R0, the PC is restored from PR, and processing is resumed from the address indicated by the PC. This instruction enables a return to be made from a subroutine procedure called by a BSR or JSR instruction to the origin of the call.

Note
This is not a delayed branch instruction.

Operation

void RTVN (int m)
{
  R[0] = R[m];
  PC = PR;
}

Possible Exceptions

Slot illegal instruction exception

Description
Clears the MACH and MACL registers.

Operation

void CLRMAC (void)
{
  MACH = 0;
  MACL = 0;
  PC += 2;
}

Description
Clears the S bit to 0.

Operation

void CLRS (void)
{
  S = 0;
  PC += 2;
}

Description
Clears the T bit.

Operation

void CLRT (void)
{
  T = 0;
  PC += 2;
}

Description
Accesses the instruction cache at the effective address indicated by the contents of Rn. When the cache is hit, the corresponding cache block is invalidated (the V bit is cleared to 0). At this time, write-back is not performed. No operation is performed in the case of a cache miss or access to a non-cache area.

Note
When a program is overwriting RAM to modify its own execution, the corresponding block of the instruction cache should be invalidated by the ICBI instruction. This prevents execution of the program from the instruction cache, where the non-overwritten instructions are stored.

Operation

void ICBI (int n)
{
  invalidate_instruction_cache_block (R[n]);
  PC += 2;
}

Possible Exceptions

Instruction TLB multiple-hit exception

Instruction TLB miss exception

Instruction TLB protection violation exception

Instruction address error

Slot illegal instruction exception

Exceptions may occur when invalidation is not performed.

Description
The register bank entry indicated by the contents of general register Rm is transferred to general register R0. The register bank number and register stored in the bank are specified by general register Rm.


Note
The architecture supports a maximum of 512 banks. However, the number of banks differs depending on the product.

Operation

void LDBANK (int m)
{
  R[0] = Read_Bank_32 (R[m]);
  PC += 2;
}

Description
Stores the source operand in the control register SR.

Note
This instruction is only usable in privileged mode. Issuing this instruction in user mode will cause an illegal instruction exception.

Operation

void LDCSR (int m)
{
  #if SH1 || SH2 || SH2 || SH3
  SR = R[m] & 0x0FFF0FFF;

  #elif SH2A
  SR = R[m] & 0x000063F3;

  #elif SH4 || SH4A
  SR = R[m] & 0x700083F3;

  #endif

  PC += 2;
}

Possible Exceptions

General illegal instruction exception

Slot illegal instruction exception

Description
Stores the source operand in the control register SR.

Note
This instruction is only usable in privileged mode. Issuing this instruction in user mode will cause an illegal instruction exception.

Operation

void LDCMSR (int m)
{
  #if SH1 || SH2 || SH2 || SH3
  SR = Read_32 (R[m]) & 0x0FFF0FFF;

  #elif SH2A
  SR = Read_32 (R[m]) & 0x000063F3;

  #elif SH4 || SH4A
  SR = Read_32 (R[m]) & 0x700083F3;

  #endif

  R[m] += 4;
  PC += 2;
}

Possible Exceptions

Data TLB multiple-hit exception

Data TLB miss exception

Data TLB protection violation exception

Data address error

General illegal instruction exception

Slot illegal instruction exception

Description
Stores a source operand in control register TBR.

Operation

void LDCTBR (int m)
{
  TBR = R[m];
  PC += 2;
}

Description
Stores a source operand in control register GBR.

Note
This instruction can also be issued in user mode.

Operation

void LDCGBR (int m)
{
  GBR = R[m];
  PC += 2;
}

Description
Stores a source operand in control register GBR.

Note
This instruction can also be issued in user mode.

Operation

void LDCMGBR (int m)
{
  GBR = Read_32 (R[m]);
  R[m] += 4;
  PC += 2;
}

Possible Exceptions

Data TLB multiple-hit exception

Data TLB miss exception

Data TLB protection violation exception

Data address error

Description
Stores a source operand in control register VBR.

Operation

void LDCVBR (int m)
{
  VBR = R[m];
  PC += 2;
}

Possible Exceptions

General illegal instruction exception

Slot illegal instruction exception

Description
Stores a source operand in control register VBR.

Operation

void LDCMVBR (int m)
{
  VBR = Read_32 (R[m]);
  R[m] += 4;
  PC += 2;
}

Possible Exceptions

Data TLB multiple-hit exception

Data TLB miss exception

Data TLB protection violation exception

Data address error

General illegal instruction exception

Slot illegal instruction exception

Description
Stores a source operand in control register MOD.

Note
On the SH-DSP the latency of this instruction is 1 cycle.

Operation

void LDCMOD (int m)
{
  MOD = R[m];
  PC += 2;
}

Description
Stores a source operand in control register MOD.

Note
On the SH-DSP the latency of this instruction is 3 cycles.

Operation

void LDCMMOD (int m)
{
  MOD = Read_32 (R[m]);
  R[m] += 4;
  PC += 2;
}

Possible Exceptions

Data address error

Description
Stores a source operand in control register RE.

Note
On the SH-DSP the latency of this instruction is 1 cycle.

Operation

void LDCRE (int m)
{
  RE = R[m];
  PC += 2;
}

Description
Stores a source operand in control register RE.

Note
On the SH-DSP the latency of this instruction is 3 cycles.

Operation

void LDCMRE (int m)
{
  RE = Read_32 (R[m]);
  R[m] += 4;
  PC += 2;
}

Possible Exceptions

Data address error

Description
Stores a source operand in control register RS.

Note
On the SH-DSP the latency of this instruction is 1 cycle.

Operation

void LDCRS (int m)
{
  RS = R[m];
  PC += 2;
}

Description
Stores a source operand in control register RS.

Note
On the SH-DSP the latency of this instruction is 3 cycles.

Operation

void LDCMRS (int m)
{
  RS = Read_32 (R[m]);
  R[m] += 4;
  PC += 2;
}

Possible Exceptions

Data address error

Description
Stores a source operand in control register SGR.

Note
Not sure whether it is also available on SH4. It is not marked as new instruction for SH4A but is also not listed in SH4 manuals.

Operation

void LDCSGR (int m)
{
  SGR = R[m];
  PC += 2;
}

Possible Exceptions

General illegal instruction exception

Slot illegal instruction exception

Description
Stores a source operand in control register SGR.

Note
Not sure whether it is also available on SH4. It is not marked as new instruction for SH4A but is also not listed in SH4 manuals.

Operation

void LDCMSGR (int m)
{
  SGR = Read_32 (R[m]);
  R[m] += 4;
  PC += 2;
}

Possible Exceptions

Data TLB multiple-hit exception

Data TLB miss exception

Data TLB protection violation exception

Data address error

General illegal instruction exception

Slot illegal instruction exception

Description
Stores a source operand in control register SSR.

Operation

void LDCSSR (int m)
{
  SSR = R[m],
  PC += 2;
}

Possible Exceptions

General illegal instruction exception

Slot illegal instruction exception

Description
Stores a source operand in control register SSR.

Operation

void LDCMSSR (int m)
{
  SSR = Read_32 (R[m]);
  R[m] += 4;
  PC += 2;
}

Possible Exceptions

Data TLB multiple-hit exception

Data TLB miss exception

Data TLB protection violation exception

Data address error

General illegal instruction exception

Slot illegal instruction exception

Description
Stores a source operand in control register SPC.

Operation

void LDCSPC (int m)
{
  SPC = R[m];
  PC += 2;
}

Possible Exceptions

General illegal instruction exception

Slot illegal instruction exception

Description
Stores a source operand in control register SPC.

Operation

void LDCMSPC (int m)
{
  SPC = Read_32 (R[m]);
  R[m] += 4;
  PC += 2;
}

Possible Exceptions

Data TLB multiple-hit exception

Data TLB miss exception

Data TLB protection violation exception

Data address error

General illegal instruction exception

Slot illegal instruction exception

Description
Stores a source operand in control register DBR.

Operation

void LDCDBR (int m)
{
  DBR = R[m];
  PC += 2;
}

Possible Exceptions

General illegal instruction exception

Slot illegal instruction exception

Description
Stores a source operand in control register DBR.

Operation

void LDCMDBR (int m)
{
  DBR = Read_32 (R[m]);
  R[m] += 4;
  PC += 2;
}

Possible Exceptions

Data TLB multiple-hit exception

Data TLB miss exception

Data TLB protection violation exception

Data address error

General illegal instruction exception

Slot illegal instruction exception

Description
Stores a source operand in banked general register. Rn_BANK0 is accessed when the RB bit in the SR register is 1, and Rn_BANK1 is accessed when this bit is 0.

Operation

void LDCRn_BANK (int m)
{
  Rn_BANK = R[m];
  PC += 2;
}

Possible Exceptions

General illegal instruction exception

Slot illegal instruction exception

Description
Stores a source operand in banked general register. Rn_BANK0 is accessed when the RB bit in the SR register is 1, and Rn_BANK1 is accessed when this bit is 0.

Operation

void LDCMRn_BANK (int m)
{
  Rn_BANK = Read_32 (R[m]);
  R[m] += 4;
  PC += 2;
}

Possible Exceptions

Data TLB multiple-hit exception

Data TLB miss exception

Data TLB protection violation exception

Data address error

General illegal instruction exception

Slot illegal instruction exception

Description
Stores the effective address of the source operand in the repeat end register RE. The effective address is an address specified by PC + displacement. The PC is the address four bytes after this instruction. The 8-bit displacement is sign-extended and doubled. Consequently, the relative interval from the branch destination is -256 to +254 bytes.

Note
The effective address value designated for the RE reregister is different from the actual repeat end address. Refer to RS and RE Design Rules, for more information.

When this instruction is arranged immediately after the delayed branch instruction, PC becomes the "first address +2" of the branch destination.

On the SH-DSP the latency of this instruction is 1 cycle.

Operation

void LDRE (int d)
{
  long disp;

  if ((d & 0x80) == 0)
    disp = (0x000000FF & (long)d);
  else
    disp = (0xFFFFFF00 | (long)d);

  RE = PC + (disp << 1);
  PC += 2;
}

Example

    ldrs   start     ! Set repeat start address to RS
    ldre   end       ! Set repeat end address to RE
    setrc  #32       ! Repeat 32 times from  to 
    ...
start:
    
    ...
    ...
    ...
end:
    
    ...

Description
Stores the effective address of the source operand in the repeat start register RS. The effective address is an address specified by PC + displacement. The PC is the address four bytes after this instruction. The 8-bit displacement is sign-extended and doubled. Consequently, the relative interval from the branch destination is -256 to +254 bytes.

Note
When the instructions of the repeat (loop) program are below 3, the effective address value designated for the RS register is different from the actual repeat start address. Refer to "RS and RE setting rule", for more information. If this

instruction is arranged immediately after the delayed branch instruction, the PC becomes "the first address +2" of the branch destination.

On the SH-DSP the latency of this instruction is 1 cycle.

Operation

void LDRS (int d)
{
  long disp;

  if ((d & 0x80) == 0)
    disp = (0x000000FF & (long)d);
  else
    disp = (0xFFFFFF00 | (long)d);

  RS = PC + (disp << 1);
  PC += 2;
}

Example

    ldrs   start     ! Set repeat start address to RS
    ldre   end       ! Set repeat end address to RE
    setrc  #32       ! Repeat 32 times from  to 
    ...
start:
    
    ...
    ...
    ...
end:
    
    ...

Description
Stores the source operand into the system register MACH.

Note
On SH1, only the lower 10 bits are stored in MACH.

On SH4, when an LDS to MAC* is followed by an STS.L MAC*,@-Rn instruction, the latency of the LDS to MAC* is 4 cycles. When an LDS to MAC* is followed by MAC.W/MAC.L, the latency of the LDS to MAC* is 1 cycle.

Operation

void LDSMACH (int m)
{
  MACH = R[m];

  #if SH1
  if ((MACH & 0x00000200) == 0)
    MACH &= 0x000003FF; 
  else
    MACH |= 0xFFFFFC00;
  #endif

  PC += 2;
}

Description
Stores the source operand into the system register MACH.

Note
On SH4, when an LDS to MAC* is followed by an STS.L MAC*,@-Rn instruction, the latency of the LDS to MAC* is 4 cycles. When an LDS to MAC* is followed by MAC.W/MAC.L, the latency of the LDS to MAC* is 1 cycle.

Operation

void LDSMMACH (int m)
{
  MACH = Read_32 (R[m]);

  #if SH1
  if ((MACH & 0x00000200) == 0)
    MACH &= 0x000003FF; 
  else
    MACH |= 0xFFFFFC00;
  #endif

  R[m] += 4;
  PC += 2;
}

Possible Exceptions

Data TLB multiple-hit exception

Data TLB miss exception

Data TLB protection violation exception

Data address error

Description
Stores the source operand into the system register MACL.

Note
On SH4, when an LDS to MAC* is followed by an STS.L MAC*,@-Rn instruction, the latency of the LDS to MAC* is 4 cycles. When an LDS to MAC* is followed by MAC.W/MAC.L, the latency of the LDS to MAC* is 1 cycle.

Operation

void LDSMACL (int m)
{
  MACL = R[m];
  PC += 2;
}

Description
Stores the source operand into the system register MACL.

Note
On SH4, when an LDS to MAC* is followed by an STS.L MAC*,@-Rn instruction, the latency of the LDS to MAC* is 4 cycles. When an LDS to MAC* is followed by MAC.W/MAC.L, the latency of the LDS to MAC* is 1 cycle.

Operation

void LDSMMACL (int m)
{
  MACL = Read_32 (R[m]);
  R[m] += 4;
  PC += 2;
}

Possible Exceptions

Data TLB multiple-hit exception

Data TLB miss exception

Data TLB protection violation exception

Data address error

Description
Stores the source operand into the system register PR.

Operation

void LDSPR (int m)
{
  PR = R[m];
  PC += 2;
}

Description
Stores the source operand into the system register PR.

Operation

void LDSMPR (int m)
{
  PR = Read_32 (R[m]);
  R[m] += 4;
  PC += 2;
}

Possible Exceptions

Data TLB multiple-hit exception

Data TLB miss exception

Data TLB protection violation exception

Data address error

Description
Stores the source operand into the DSP register DSR.

Operation

void LDSDSR (int m)
{
  DSR = R[m] & 0x0000000F;
  PC += 2;
}

Description
Stores the source operand into the DSP register DSR.

Note
On the SH-DSP the latency of this instruction is 1 cycle.

Operation

void LDSMDSR (int m)
{
  DSR = Read_32 (R[m]) & 0x0000000F;
  R[m] += 4;
  PC += 2;
}

Possible Exceptions

Data address error

Description
Stores the source operand into the DSP register A0. The MSB of the data is copied into A0G.

Operation

void LDSA0 (int m)
{
  A0 = R[m];

  if ((A0 & 0x80000000) == 0)
    A0G = 0x00;
  else
    A0G = 0xFF;

  PC+=2;
}

Description
Stores the source operand into the DSP register A0. The MSB of the data is copied into A0G.

Operation

void LDSMA0 (int m)
{
  A0 = Read_32 (R[m]);

  if ((A0 & 0x80000000) == 0)
    A0G = 0x00;
  else
    A0G = 0xFF;

  R[m] += 4;
  PC += 2;
}

Possible Exceptions

Data address error

Description
Stores the source operand into the DSP register X0.

Operation

void LDSX0 (int m)
{
  X0 = R[m];
  PC += 2;
}

Description
Stores the source operand into the DSP register X0.

Operation

void LDSMX0 (int m)
{
  X0 = Read_32 (R[m]);
  R[m] += 4;
  PC += 2;
}

Possible Exceptions

Data address error

Description
Stores the source operand into the DSP register X1.

Operation

void LDSX1 (int m)
{
  X1 = R[m];
  PC += 2;
}

Description
Stores the source operand into the DSP register X1.

Operation

void LDSMX1 (int m)
{
  X1 = Read_32 (R[m]);
  R[m] += 4;
  PC += 2;
}

Possible Exceptions

Data address error

Description
Stores the source operand into the DSP register Y0.

Operation

void LDSY0 (int m)
{
  Y0 = R[m];
  PC += 2;
}

Description
Stores the source operand into the DSP register Y0.

Operation

void LDSMY0 (int m)
{
  Y0 = Read_32 (R[m]);
  R[m] += 4;
  PC += 2;
}

Possible Exceptions

Data address error

Description
Stores the source operand into the DSP register Y1.

Operation

void LDSY1 (int m)
{
  Y1 = R[m];
  PC += 2;
}

Description
Stores the source operand into the DSP register Y1.

Operation

void LDSMY1 (int m)
{
  Y1 = Read_32 (R[m]);
  R[m] += 4;
  PC += 2;
}

Possible Exceptions

Data address error

Description
Loads the contents of the PTEH/PTEL registers into the TLB (translation lookaside buffer) specified by MMUCR.URC (random counter field in the MMC control register).

LDTLB is a privileged instruction, and can only be used in privileged mode. Use of this instruction in user mode will cause an illegal instruction exception.

Note
As this instruction loads the contents of the PTEH/PTEL registers into a TLB, it should be used either with the MMU disabled, or in the P1 or P2 virtual space with the MMU enabled (see the MMU section of the applicable hardware manual for details).

After this instruction is issued, there must be at least one instruction between the LDTLB instruction and issuance of an instruction relating to address to the P0, U0, and P3 areas (i.e. BRAF, BSRF, JMP, JSR, RTS, or RTE).

If the instruction is issued in an exception handler, it should be at least two instructions prior to an RTE instruction that terminates the handler.

Operation

void LDTLB (void)
{
  #if SH3
  TLB_tag = PTEH;
  TLB_data = PTEL;

  #elif SH4
  TLB[MMUCR.URC].ASID = PTEH & 0x000000FF;
  TLB[MMUCR.URC].VPN = (PTEH & 0xFFFFFC00) >> 10;
  TLB[MMUCR.URC].PPN = (PTEH & 0x1FFFFC00) >> 10;
  TLB[MMUCR.URC].SZ = (PTEL & 0x00000080) >> 6 | (PTEL & 0x00000010) >> 4;
  TLB[MMUCR.URC].SH = (PTEH & 0x00000002) >> 1;
  TLB[MMUCR.URC].PR = (PTEH & 0x00000060) >> 5;
  TLB[MMUCR.URC].WT = (PTEH & 0x00000001);
  TLB[MMUCR.URC].C = (PTEH & 0x00000008) >> 3;
  TLB[MMUCR.URC].D = (PTEH & 0x00000004) >> 2;
  TLB[MMUCR.URC].V = (PTEH & 0x00000100) >> 8;

  #endif

  PC += 2;
}

Possible Exceptions

General illegal instruction exception

Slot illegal instruction exception

Description
Stores the contents of general register R0 in the memory location indicated by effective address Rn. This instruction differs from other store instructions as follows.

If write-back is selected for the accessed memory, and a cache miss occurs, the cache block will be allocated but an R0 data write will be performed to that cache block without performing a block read. Other cache block contents are undefined.

Operation

void MOVCAL (int n)
{
  if (is_write_back_memory (R[n]) && look_up_in_operand_cache (R[n]) == MISS)
    allocate_operand_cache_block (R[n]);

  Write_32 (R[n], R[0]);
  PC += 2;
}

Possible Exceptions

Data TLB multiple-hit exception

Data TLB miss exception

Data TLB protection violation exception

Initial page write exception

Data address error

Note
Increments the program counter (PC), advancing the processing flow to execution of the next instruction.

Operation

void NOP (void)
{
  PC += 2;
}

Description
Accesses data using the contents indicated by effective address Rn. In the case of a hit in the cache, the corresponding cache block is invalidated (the V bit is cleared to 0). If there is unwritten information (U bit = 1), write-back is not performed even if write-back mode is selected. No operation is performed in the case of a cache miss or an access to a non-cache area.

Operation

void OCBI (int n)
{
  invalidate_operand_cache_block (R[n]);
  PC += 2;
}

Possible Exceptions

Data TLB multiple-hit exception

Data TLB miss exception

Data TLB protection violation exception

Initial page write exception

Data address error

Note that the above exceptions are generated even if OCBI does not operate.

Description
Accesses data using the contents indicated by effective address Rn. If the cache is hit and there is unwritten information (U bit = 1), the corresponding cache block is written back to external memory and that block is invalidated (the V bit is cleared to 0). If there is no unwritten information (U bit = 0), the block is simply invalidated. No operation is performed in the case of a cache miss or an access to a non-cache area.

Operation

void OCBP (int n)
{
  if (is_dirty_block (R[n]))
    write_back (R[n])

  invalidate_operand_cache_block (R[n]);
  PC += 2;
}

Possible Exceptions

Data TLB multiple-hit exception

Data TLB miss exception

Data TLB protection violation exception

Data address error

Note that the above exceptions are generated even if OCBP does not operate.

Description
Accesses data using the contents indicated by effective address Rn. If the cache is hit and there is unwritten information (U bit = 1), the corresponding cache block is written back to external memory and that block is cleaned (the U bit is cleared to 0). In other cases (i.e. in the case of a cache miss or an access to a non-cache area, or if the block is already clean), no operation is performed.

Operation

void OCBWB (int n)
{
  if (is_dirty_block (R[n]))
    write_back (R[n]);

  PC += 2;
}

Possible Exceptions

Data TLB multiple-hit exception

Data TLB miss exception

Data TLB protection violation exception

Data address error

Note that the above exceptions are generated even if OCBWB does not operate.

Description
SH4 and SH4A
Reads a 32-byte data block starting at a 32-byte boundary into the operand cache. The lower 5 bits of the address specified by Rn are masked to zero.
This instruction is also used to trigger a Store Queue write-back operation if the specified address points to the Store Queue area. For more information refer to Store Queues in the manual.

SH3 and SH2A
Reads a 16-byte data block into the cache. The address specified by Rn should be on 32-bit boundary. No address related error is detected in this instruction. In case of an error, the instruction operates as NOP.

Note
On products with no cache, this instruction is handled as a NOP instruction.

Operation

void PREF (int n)
{
  prefetch_operand_cache_block (R[n]);
  PC += 2;
}

Possible Exceptions

Data TLB multiple-hit exception

Description
Reads a 32-byte block of data starting at a 32-byte boundary within the instruction cache. The lower 5 bits of the address specified by Rn are masked by zeroes.

This instruction does not generate data address error and MMU exceptions. In the event of an error, the PREFI instruction is treated as an NOP (no operation) instruction.

When the address to be prefetched is missing from UTLB or is protected, the PREFI instruction is treated as an NOP instruction and a TLB exception does not occur.

Note
This instruction can be used before the SLEEP command is issued to prefetch instructions for execution on return from the SLEEP state.

Operation

void PREFI (int n)
{
  prefetch_instruction_cache_block (R[n]);
  PC += 2;
}

Possible Exceptions

Slot illegal instruction exception

Description
Restores the last register saved to a register bank.

Note
The issue cycle count is 19 when a bank overflow has occured and the registers are restored from the stack.

Operation

void RESBANK (void)
{
  int m;  // Number of register bank to which a save was last performed.

  if (BO == 0)
  {
    PR = Register_Bank[m].PR_BANK;
    GBR = Register_Bank[m].GBR_BANK;
    MACL = Register_Bank[m].MACL_BANK;
    MACH = Register_Bank[m].MACH_BANK;

    for (int i = 0; i <= 14; i++)
      R[i] = Register_Bank[m].R_BANK[i];
  }
  else
  {
    for (int i = 0; i <= 14; i++)
    {
      R[i] = Read_32 (R[15]);
      R[15] += 4;
    }

    PR = Read_32 (R[15]);
    R[15] += 4;
    GBR = Read_32 (R[15]);
    R[15] += 4;
    MACH = Read_32 (R[15]);
    R[15] += 4;
    MACL = Read_32 (R[15]);
    R[15] += 4;
  }

  PC += 2;
}

Description
Returns from an exception or interrupt handling routine by restoring the PC and SR values. Program execution continues from the address specified by the restored PC value.

On SH3 and SH4 the PC and SR values are restored from SPC and SSR. The SR value accessed by the instruction in the RTE delay slot is the value restored from SSR by the RTE instruction. The SR and MD values defined prior to RTE execution are used to fetch the instruction in the RTE delay slot.

On SH1, SH2 and SH2A the PC and SR values are from the stack (R15).

Note
As this is a delayed branch instruction, the instruction following the RTE instruction is executed before the branch destination instruction.

Interrupts are not accepted between this instruction and the following instruction. An exception must not be generated by the instruction in this instruction's delay slot. If the following instruction is a branch instruction, it is identified as a slot illegal instruction.

If this instruction is located in the delay slot immediately following a delayed branch instruction, it is identified as a slot illegal instruction.

On SH3 and SH4 the SR value accessed by the instruction in the RTE delay slot is the value restored from SSR by the RTE instruction. The SR and MD values defined prior to RTE execution are used to fetch the instruction in the RTE delay slot.

Operation

void RTE (void)
{
  unsigned long temp = PC;

  #if SH1 || SH2 || SH2A
  PC = Read_32 (R[15]);
  R[15] += 4;
  SR = Read_32 (R[15]) & 0x000063F3;
  R[15] += 4;

  #elif SH3 || SH4 || SH4A
  SR = SSR;
  PC = SPC;

  #endif

  Delay_Slot (temp + 2);
}

Possible Exceptions

General illegal instruction exception

Slot illegal instruction exception

Description
Sets the repeat count to the SR register's RC counter. The bottom 12 bits of the general register Rn are used as the repeat count. Set repeat control flags to RF1, RF0 bits of the SR register. Use of the SETRC instruction is subject to any limitations. Refer to the DSP Repeat (Loop) Control section of the manual for more information.


Note
On the SH-DSP the latency of this instruction is 1 cycle.

Operation

void SETRC (int m)
{
  long temp = (R[m] & 0x00000FFF) << 16;
  SR &= 0x00000FF3;
  SR |= temp;
  RF1 = Repeat_Control_Flag1;
  RF0 = Repeat_Control_Flag0;
  PC += 2;
}

Example

    ldrs   start     ! Set repeat start address to RS
    ldre   end       ! Set repeat end address to RE
    setrc  r14       ! Repeat n times from  to 
    ...
start:
    
    ...
    ...
    ...
end:
    
    ...

Description
Sets the repeat count to the SR register's RC counter. The 8-bit immediate value is zero-extended and used as the repeat count. Set repeat control flags to RF1, RF0 bits of the SR register. Use of the SETRC instruction is subject to any limitations. Refer to the DSP Repeat (Loop) Control section of the manual for more information.


Note
On the SH-DSP the latency of this instruction is 1 cycle.

Operation

void SETRCI (int i)
{
  long temp = ((long)i & 0x000000FF) << 16;
  SR &= 0x00000FFF;
  SR |= temp;
  RF1 = Repeat_Control_Flag1;
  RF0 = Repeat_Control_Flag0;
  PC += 2;
}

Example

    ldrs   start     ! Set repeat start address to RS
    ldre   end       ! Set repeat end address to RE
    setrc  #32       ! Repeat 32 times from  to 
    ...
start:
    
    ...
    ...
    ...
end:
    
    ...

Description
Sets the S bit to 1.

Operation

void SETS (void)
{
  S = 1;
  PC += 2;
}

Description
Sets the T bit to 1.

Operation

void SETT (void)
{
  T = 1;
  PC += 2;
}

Description
Places the CPU in the power-down state.

In power-down mode, the CPU retains its internal state, but immediately stops executing instructions and waits for an interrupt request. When it receives an interrupt request, the CPU exits the power-down state.

SLEEP is a privileged instruction, and can only be used in privileged mode. Use of this instruction in user mode will cause an illegal instruction exception.

Note
SLEEP performance depends on the standby control register (STBCR). See Power-Down Modes in the target product's hardware manual, for details.

The number of cycles given is for the transition to sleep mode. "ud" means the number of cycles is undefined.

Some SH4 implementations have a hardware bug which restricts the instructions that should follow this instruction for safe operation. There are two recommended workarounds:

Put 8 NOP instructions following the SLEEP instruction.

Put 5 "OR R0,R0" instructions following the SLEEP instruction

For more information see the document "tnsh7456ae.pdf".

Operation

void SLEEP (void)
{
  Sleep_standby();
}

Possible Exceptions

General illegal instruction exception

Slot illegal instruction exception

Description
R0 is transferred to the register bank entry indicated by the contents of general register Rn. The register bank number and register stored in the bank are specified by general register Rn.


Note
The architecture supports a maximum of 512 banks. However, the number of banks differs depending on the product.

Operation

void STBANK (int n)
{
  Write_Bank_32 (R[n], R[0])
  PC += 2;
}

Description
Stores control register SR in the destination.

Note
This instruction is only usable in privileged mode. Issuing this instruction in user mode will cause an illegal instruction exception.

Operation

void STCSR (int n)
{
  R[n] = SR;
  PC += 2;
}

Possible Exceptions

General illegal instruction exception

Slot illegal instruction exception

Description
Stores control register SR in the destination.

Note
This instruction is only usable in privileged mode. Issuing this instruction in user mode will cause an illegal instruction exception.

Operation

void STCMSR (int n)
{
  R[n] -= 4;
  Write_32 (R[n], SR);
  PC += 2;
}

Possible Exceptions

Data TLB multiple-hit exception

Data TLB miss exception

Data TLB protection violation exception

Initial page write exception

Data address error

General illegal instruction exception

Slot illegal instruction exception

Description
Stores control register TBR in the destination.

Operation

void STCTBR (int n)
{
  R[n] = TBR;
  PC += 2;
}

Description
Stores control register GBR in the destination.

Note
This instruction can also be issued in user mode.

Operation

STCGBR (int n)
{
  R[n] = GBR;
  PC += 2;
}

Description
Stores control register GBR in the destination.

Note
This instruction can also be issued in user mode.

Operation

void STCMGBR (int n)
{
  R[n] -= 4;
  Write_32 (R[n], GBR);
  PC += 2;
}

Possible Exceptions

Data TLB multiple-hit exception

Data TLB miss exception

Data TLB protection violation exception

Initial page write exception

Data address error

Description
Stores control register VBR in the destination.

Operation

void STCVBR (int n)
{
  R[n] = VBR;
  PC += 2;
}

Possible Exceptions

General illegal instruction exception

Slot illegal instruction exception

Description
Stores control register VBR in the destination.

Operation

void STCMVBR (int n)
{
  R[n] -= 4;
  Write_32 (R[n], VBR);
  PC += 2;
}

Possible Exceptions

Data TLB multiple-hit exception

Data TLB miss exception

Data TLB protection violation exception

Initial page write exception

Data address error

General illegal instruction exception

Slot illegal instruction exception

Description
Stores control register MOD in the destination.

Operation

void STCMOD (int n)
{
  R[n] = MOD;
  PC += 2;
}

Description
Stores control register MOD in the destination.

Note
On the SH-DSP the latency of this instruction is 2 cycles.

Operation

void STCMMOD (int n)
{
  R[n] -= 4;
  Write_32 (R[n], MOD);
  PC += 2;
}

Possible Exceptions

Data address error

Description
Stores control register RE in the destination.

Operation

void STCRE (int n)
{
  R[n] = RE;
  PC += 2;
}

Description
Stores control register RE in the destination.

Note
On the SH-DSP the latency of this instruction is 2 cycles.

Operation

void STCMRE (int n)
{
  R[n] -= 4;
  Write_32 (R[n], RE);
  PC += 2;
}

Possible Exceptions

Data address error

Description
Stores control register RS in the destination.

Operation

void STCRS (int n)
{
  R[n] = RS;
  PC += 2;
}

Description
Stores control register RS in the destination.

Note
On the SH-DSP the latency of this instruction is 2 cycles.

Operation

void STCMRS (int n)
{
  R[n] -= 4;
  Write_32 (R[n], RS);
  PC += 2;
}

Possible Exceptions

Data address error

Description
Stores control register SGR in the destination.

Operation

void STCSGR (int n)
{
  R[n] = SGR;
  PC += 2;
}

Possible Exceptions

General illegal instruction exception

Slot illegal instruction exception

Description
Stores control register SGR in the destination.

Operation

void STCMSGR (int n)
{
  R[n] -= 4;
  Write_32 (R[n], SGR);
  PC += 2;
}

Possible Exceptions

Data TLB multiple-hit exception

Data TLB miss exception

Data TLB protection violation exception

Initial page write exception

Data address error

General illegal instruction exception

Slot illegal instruction exception

Description
Stores control register SSR in the destination.

Operation

void STCSSR (int n)
{
  R[n] = SSR;
  PC += 2;
}

Possible Exceptions

General illegal instruction exception

Slot illegal instruction exception

Description
Stores control register SSR in the destination.

Operation

void STCMSSR (int n)
{
  R[n] -= 4;
  Write_32 (R[n], SSR);
  PC += 2;
}

Possible Exceptions

Data TLB multiple-hit exception

Data TLB miss exception

Data TLB protection violation exception

Initial page write exception

Data address error

General illegal instruction exception

Slot illegal instruction exception

Description
Stores control register SPC in the destination.

Operation

void STCSPC (int n)
{
  R[n] = SPC;
  PC += 2;
}

Possible Exceptions

General illegal instruction exception

Slot illegal instruction exception

Description
Stores control register SPC in the destination.

Operation

void STCMSPC (int n)
{
  R[n] -= 4;
  Write_32 (R[n], SPC);
  PC += 2;
}

Possible Exceptions

Data TLB multiple-hit exception

Data TLB miss exception

Data TLB protection violation exception

Initial page write exception

Data address error

General illegal instruction exception

Slot illegal instruction exception

Description
Stores control register DBR in the destination.

Operation

void STCDBR (int n)
{
  R[n] = DBR;
  PC += 2;
}

Possible Exceptions

General illegal instruction exception

Slot illegal instruction exception

Description
Stores control register DBR in the destination.

Operation

void STCMDBR (int n)
{
  R[n] -= 4;
  Write_32 (R[n], DBR);
  PC += 2;
}

Possible Exceptions

Data TLB multiple-hit exception

Data TLB miss exception

Data TLB protection violation exception

Initial page write exception

Data address error

General illegal instruction exception

Slot illegal instruction exception

Description
Stores a banked general register in the destination. Rn_BANK0 is accessed when the RB bit in the SR register is 1, and Rn_BANK1 is accessed when this bit is 0.

Operation

void STCRm_BANK (int n)
{
  R[n] = Rm_BANK;
  PC += 2;
}

Possible Exceptions

General illegal instruction exception

Slot illegal instruction exception

Description
Stores a banked general register in the destination. Rn_BANK0 is accessed when the RB bit in the SR register is 1, and Rn_BANK1 is accessed when this bit is 0.

Operation

void STCMRm_BANK (int n)
{
  R[n] -= 4;
  Write_32 (R[n], Rm_BANK);
  PC += 2;
}

Possible Exceptions

Data TLB multiple-hit exception

Data TLB miss exception

Data TLB protection violation exception

Initial page write exception

Data address error

General illegal instruction exception

Slot illegal instruction exception

Description
Stores system register MACH in the destination.

Note
On SH1, the value of bit 9 is transferred to and stored in the higher 22 bits (bits 31 to 10) of the destination.

On SH4, when an LDS to MAC* is followed by an STS.L MAC*,@-Rn instruction, the latency of the LDS to MAC* is 4 cycles.

Operation

void STSMACH (int n)
{
  R[n] = MACH;

  #if SH1
  if ((R[n] & 0x00000200) == 0)
    R[n] &= 0x000003FF; 
  else
    R[n] |= 0xFFFFFC00;

  #endif

  PC += 2;
}

Description
Stores system register MACH in the destination.

Note
On SH1, the value of bit 9 is transferred to and stored in the higher 22 bits (bits 31 to 10) of the destination.

On SH4, when an LDS to MAC* is followed by an STS.L MAC*,@-Rn instruction, the latency of the LDS to MAC* is 4 cycles.

Operation

void STSMMACH (int n)
{
  R[n] -= 4;

  #if SH1
  if ((MACH & 0x00000200) == 0)
    Write_32 (R[n], MACH & 0x000003FF);
  else
    Write_32 (R[n], MACH | 0xFFFFFC00)

  #else
  Write_32 (R[n], MACH);

  #endif

  PC += 2;
}

Possible Exceptions

Data TLB multiple-hit exception

Data TLB miss exception

Data TLB protection violation exception

Initial page write exception

Data address error

Description
Stores system register MACL in the destination.

Note
On SH4, when an LDS to MAC* is followed by an STS.L MAC*,@-Rn instruction, the latency of the LDS to MAC* is 4 cycles.

Operation

void STSMACL (int n)
{
  R[n] = MACL;
  PC += 2;
}

Description
Stores system register MACL in the destination.

Note
On SH4, when an LDS to MAC* is followed by an STS.L MAC*,@-Rn instruction, the latency of the LDS to MAC* is 4 cycles.

Operation

void STSMMACL (int n)
{
  R[n] -= 4;
  Write_32 (R[n], MACL);
  PC += 2;
}

Possible Exceptions

Data TLB multiple-hit exception

Data TLB miss exception

Data TLB protection violation exception

Initial page write exception

Data address error

Description
Stores system register PR in the destination.

Operation

void STSPR (int n)
{
  R[n] = PR;
  PC += 2;
}

Description
Stores system register PR in the destination.

Operation

void STSMPR (int n)
{
  R[n] -= 4;
  Write_32 (R[n], PR);
  PC += 2;
}

Possible Exceptions

Data TLB multiple-hit exception

Data TLB miss exception

Data TLB protection violation exception

Initial page write exception

Data address error

Description
Stores DSP register DSR in the destination.

Operation

void STSDSR (int n)
{
  R[n] = DSR;
  PC += 2;
}

Description
Stores DSP register DSR in the destination.

Operation

void STSMDSR (int n)
{
  R[n] -= 4;
  Write_32 (R[n], DSR);
  PC += 2;
}

Possible Exceptions

Data address error

Description
Stores DSP register A0 in the destination.

Operation

void STSA0 (int n)
{
  R[n] = A0;
  PC += 2;
}

Description
Stores DSP register A0 in the destination.

Operation

void STSMA0 (int n)
{
  R[n] -= 4;
  Write_32 (R[n], A0);
  PC += 2;
}

Possible Exceptions

Data address error

Description
Stores DSP register X0 in the destination.

Operation

void STSX0 (int n)
{
  R[n] = X0;
  PC += 2;
}

Description
Stores DSP register X0 in the destination.

Operation

void STSMX0 (int n)
{
  R[n] -= 4;
  Write_32 (R[n], X0);
  PC += 2;
}

Possible Exceptions

Data address error

Description
Stores DSP register X1 in the destination.

Operation

void STSX1 (int n)
{
  R[n] = X1;
  PC += 2;
}

Description
Stores DSP register X1 in the destination.

Operation

void STSMX1 (int n)
{
  R[n] -= 4;
  Write_32 (R[n], X1);
  PC += 2;
}

Possible Exceptions

Data address error

Description
Stores DSP register Y0 in the destination.

Operation

void STSY0 (int n)
{
  R[n] = Y0;
  PC += 2;
}

Description
Stores DSP register Y0 in the destination.

Operation

void STSMY0 (int n)
{
  R[n] -= 4;
  Write_32 (R[n], Y0);
  PC += 2;
}

Possible Exceptions

Data address error

Description
Stores DSP register Y1 in the destination.

Operation

void STSY1 (int n)
{
  R[n] = Y1;
  PC += 2;
}

Description
Stores DSP register Y1 in the destination.

Operation

void STSMY1 (int n)
{
  R[n] -= 4;
  Write_32 (R[n], Y1);
  PC += 2;
}

Possible Exceptions

Data address error

Description
This instruction is used to synchronize data operations. When this instruction is executed, the subsequent bus accesses are not executed until the execution of all preceding bus accesses has been completed.

Note
The SYNCO instruction can not guarantee the ordering of receipt timing which is notified by the memory-mapped peripheral resources through the method except bus when the register is changed by bus accesses. Refer to the description of each registers to guarantee this ordering.

Common example usages are:

Ordering access to memory areas which are shared with other memory users

Flushing all write buffers

Stopping memory-access operations from merging and becoming ineffective

Waiting for the completion of cache-control instructions

Operation

void SYNCO (void)
{
  synchronize_data_operaiton ();
  PC += 2;
}

Description
Starts trap exception handling. SH1, SH2 and SH2A:
The PC and SR values are stored on the stack, and the program branches to an address specified by the vector. The vector is a memory address obtained by zero-extending the 8-bit immediate data and then quadrupling it. The PC is the start address of the next instruction. TRAPA and RTE are both used together for system calls.

SH3, SH4 and SH4A:
The values of (PC + 2), SR, and R15 are saved to SPC, SSR and SGR, and 8-bit immediate data is stored in the TRA register (bits 9 to 2). The processor mode is switched to privileged mode (the MD bit in SR is set to 1), and the BL bit and RB bit in SR are set to 1. As a result, exception and interrupt requests are masked (not accepted), and the BANK1 registers (R0_BANK1 to R7_BANK1) are selected. Exception code 0x160 is written to the EXPEVT register (bits 11 to 0). The program branches to address (VBR + 0x00000100), indicated by the sum of the VBR register contents and offset 0x00000100.

Note
Some SH4 implementations have a hardware bug which restricts the instructions that should follow this instruction for safe operation. There are two recommended workarounds:

Put 8 NOP instructions following the TRAPA instruction.

Put 5 "OR R0,R0" instructions following the TRAPA instruction

For more information see the document "tnsh7456ae.pdf".

Some SH2E implementations (SH7055) have an FPU related hardware bug which affects this instruction. The recommended workaround is to align the addresses of trapa handlers to 4 bytes and not to place any FPU or FPU related instructions at addresses 4n + 2 in the handler.

Operation

void TRAPA (int i)
{
  int imm = (0x000000FF & i);

  #if SH1 || SH2 || SH2A
  R[15] -= 4;
  Write_32 (R[15], SR);
  R[15] -= 4;
  Write_32 (R[15], PC + 2);
  PC = Read_32 (VBR + (imm << 2));

  #elif SH3 || SH4 || SH4A
  TRA = imm << 2;
  SSR = SR;
  SPC = PC + 2;
  SGR = R15;
  SR.MD = 1;
  SR.BL = 1;
  SR.RB = 1;
  EXPEVT = 0x00000160;
  PC = VBR + 0x00000100;

  #endif
}

Possible Exceptions

Unconditional trap

Slot illegal instruction exception

Description
Transfers FRm contents to FRn.

Operation

void FMOV (int m, int n)
{
  FR[n] = FR[m];
  PC += 2;
}

Description
Transfers contents of memory at address indicated by Rm to FRn.

Operation

void FMOV_LOAD (int m, int n)
{
  FR[n] = Read_32 (R[m]);
  PC += 2;
}

Possible Exceptions

Data TLB multiple-hit exception

Data TLB miss exception

Data TLB protection violation exception

Data address error

Description
Transfers FRm contents to memory at address indicated by Rn.

Operation

void FMOV_STORE (int m, int n)
{
  Write_32 (R[n], FR[m]);
  PC += 2;
}

Possible Exceptions

Data TLB multiple-hit exception

Data TLB miss exception

Data TLB protection violation exception

Data address error

Initial page write exception

Description
Transfers contents of memory at address indicated by Rm to FRn, and adds 4 to Rm.

Operation

void FMOV_RESTORE (int m, int n)
{
  FR[n] = Read_32 (R[m]);
  R[m] += 4;
  PC += 2;
}

Possible Exceptions

Data TLB multiple-hit exception

Data TLB miss exception

Data TLB protection violation exception

Data address error

Description
Subtracts 4 from Rn, and transfers FRm contents to memory at address indicated by resulting Rn value.

Operation

void FMOV_SAVE (int m, int n)
{
  Write_32 (R[n] - 4, FR[m]);
  R[n] -= 4;
  PC += 2;
}

Possible Exceptions

Data TLB multiple-hit exception

Data TLB miss exception

Data TLB protection violation exception

Data address error

Initial page write exception

Description
Transfers contents of memory at address indicated by (R0 + Rm) to FRn.

Operation

void FMOV_INDEX_LOAD (int m, int n)
{
  FR[n] = Read_32 (R[0] + R[m]);
  PC += 2;
}

Possible Exceptions

Data TLB multiple-hit exception

Data TLB miss exception

Data TLB protection violation exception

Data address error

Description
Transfers FRm contents to memory at address indicated by (R0 + Rn).

Operation

void FMOV_INDEX_STORE (int m, int n)
{
  Write_32 (R[0] + R[n], FR[m]);
  PC += 2;
}

Possible Exceptions

Data TLB multiple-hit exception

Data TLB miss exception

Data TLB protection violation exception

Data address error

Initial page write exception

Description
Transfers memory contents at the address indicated by (disp + Rn) to FRn.

Operation

void FMOV_INDEX_DISP12_LOAD (int m, int n, int d)
{
  long disp = (0x00000FFF & (long)d);
  FR[n] = Read_32 (R[m] + (disp << 2));
  PC += 4;
}

Possible Exceptions

Data address error

Description
Transfers FRm contents to memory at the address indicated by (disp + Rn).

Operation

void FMOV_INDEX_DISP12_STORE (int m, int n, int d)
{
  long disp = (0x00000FFF & (long)d);
  Write_32 (R[n] + (disp << 2), FR[m]);
  PC += 4;
}

Possible Exceptions

Data address error

Description
Transfers DRm contents to DRn.

Operation

void FMOV_DR (int m, int n)
{
  DR[n >> 1] = DR[m >> 1];
  PC += 2;
}

Description
Transfers DRm contents to XDn.

Operation

void FMOV_DRXD (int m, int n)
{
  XD[n >> 1] = DR[m >> 1];
  PC += 2;
}

Description
Transfers XDm contents to DRn.

Operation

void FMOV_XDDR (int m, int n)
{
  DR[n >> 1] = XD[m >> 1];
  PC += 2;
}

Description
Transfers XDm contents to XDn.

Operation

void FMOV_XDXD (int m, int n)
{
  XD[n >> 1] = XD[m >> 1];
  PC += 2;
}

Description
Transfers contents of memory at address indicated by Rm to DRn.

Operation

void FMOV_LOAD_DR (int m, int n)
{
  DR[n >> 1] = Read_64 (R[m]);
  PC += 2;
}

Possible Exceptions

Data TLB multiple-hit exception

Data TLB miss exception

Data TLB protection violation exception

Data address error

Description
Transfers contents of memory at address indicated by Rm to XDn.

Operation

void FMOV_LOAD_XD (int m, int n)
{
  XD[n >> 1] = Read_64 (R[m]);
  PC += 2;
}

Possible Exceptions

Data TLB multiple-hit exception

Data TLB miss exception

Data TLB protection violation exception

Data address error

Description
Transfers DRm contents to memory at address indicated by Rn.

Operation

void FMOV_STORE_DR (int m, int n)
{
  Write_64 (R[n], DR[m >> 1]);
  PC += 2;
}

Possible Exceptions

Data TLB multiple-hit exception

Data TLB miss exception

Data TLB protection violation exception

Data address error

Initial page write exception

Description
Transfers contents of memory at address indicated by (R0 + Rm) to XDn.

Operation

void FMOV_STORE_XD (int m, int n)
{
  Write_64 (R[n], XD[m >> 1]);
  PC += 2;
}

Possible Exceptions

Data TLB multiple-hit exception

Data TLB miss exception

Data TLB protection violation exception

Data address error

Initial page write exception

Description
Transfers contents of memory at address indicated by Rm to DRn, and adds 8 to Rm.

Operation

void FMOV_RESTORE_DR (int m, int n)
{
  DR[n >> 1] = Read_64 (R[m]);
  R[m] += 8;
  PC += 2;
}

Possible Exceptions

Data TLB multiple-hit exception

Data TLB miss exception

Data TLB protection violation exception

Data address error

Description
Transfers contents of memory at address indicated by Rm to XDn, and adds 8 to Rm.

Operation

void FMOV_RESTORE_XD (int m, int n)
{
  XD[n >> 1] = Read_64 (R[m]);
  R[m] += 8;
  PC += 2;
}

Possible Exceptions

Data TLB multiple-hit exception

Data TLB miss exception

Data TLB protection violation exception

Data address error

Description
Subtracts 8 from Rn, and transfers DRm contents to memory at address indicated by resulting Rn value.

Operation

void FMOV_SAVE_DR (int m, int n)
{
  Write_64 (R[n] - 8, DR[m >> 1]);
  R[n] -= 8;
  PC += 2;
}

Possible Exceptions

Data TLB multiple-hit exception

Data TLB miss exception

Data TLB protection violation exception

Data address error

Initial page write exception

Description
Subtracts 8 from Rn, and transfers XDm contents to memory at address indicated by resulting Rn value.

Operation

void FMOV_SAVE_XD (int m, int n)
{
  Write_64 (R[n] - 8, XD[m >> 1]);
  R[n] -= 8;
  PC += 2;
}

Possible Exceptions

Data TLB multiple-hit exception

Data TLB miss exception

Data TLB protection violation exception

Data address error

Initial page write exception