Data Transfer Instructions

SH1 SH2 SH3 SH4 SH4A SH2A
mov Rm,Rn
Rm -> Rn
0110nnnnmmmm0011
MT MT
1 1 1 1 1 1
1 1 1 0 1 0
SH1 SH2 SH3 SH4 SH4A SH2A
mov #imm,Rn
imm -> sign extension -> Rn
1110nnnniiiiiiii
EX MT
1 1 1 1 1 1
1 1 1 1 1 1
SH2A
movi20 #imm20,Rn
imm -> sign extension -> Rn
0000nnnniiii0000 iiiiiiiiiiiiiiii
1
1
SH2A
movi20s #imm20,Rn
imm << 8 -> sign extension -> Rn
0000nnnniiii0001 iiiiiiiiiiiiiiii
1
1
SH1 SH2 SH3 SH4 SH4A SH2A
mova @(disp,PC),R0
(disp*4) + (PC & 0xFFFFFFFC) + 4 -> R0
11000111dddddddd
EX LS
1 1 1 1 1 1
1 1 1 1 1 1
SH1 SH2 SH3 SH4 SH4A SH2A
mov.w @(disp,PC),Rn
(disp*2 + PC + 4) -> sign extension -> Rn
1001nnnndddddddd
LS LS
1 1 1 1 1 1
1 1 1 2 1 2
SH1 SH2 SH3 SH4 SH4A SH2A
mov.l @(disp,PC),Rn
(disp*4 + (PC & 0xFFFFFFFC) + 4) -> sign extension -> Rn
1101nnnndddddddd
LS LS
1 1 1 1 1 1
1 1 1 2 1 2
SH1 SH2 SH3 SH4 SH4A SH2A
mov.b @Rm,Rn
(Rm) -> sign extension -> Rn
0110nnnnmmmm0000
LS LS
1 1 1 1 1 1
1 1 1 2 1 2
SH1 SH2 SH3 SH4 SH4A SH2A
mov.w @Rm,Rn
(Rm) -> sign extension -> Rn
0110nnnnmmmm0001
LS LS
1 1 1 1 1 1
1 1 1 2 1 2
SH1 SH2 SH3 SH4 SH4A SH2A
mov.l @Rm,Rn
(Rm) -> Rn
0110nnnnmmmm0010
LS LS
1 1 1 1 1 1
1 1 1 2 1 2
SH1 SH2 SH3 SH4 SH4A SH2A
mov.b Rm,@Rn
Rm -> (Rn)
0010nnnnmmmm0000
LS LS
1 1 1 1 1 1
1 1 1 1 1 0
SH1 SH2 SH3 SH4 SH4A SH2A
mov.w Rm,@Rn
Rm -> (Rn)
0010nnnnmmmm0001
LS LS
1 1 1 1 1 1
1 1 1 1 1 0
SH1 SH2 SH3 SH4 SH4A SH2A
mov.l Rm,@Rn
Rm -> (Rn)
0010nnnnmmmm0010
LS LS
1 1 1 1 1 1
1 1 1 1 1 0
SH1 SH2 SH3 SH4 SH4A SH2A
mov.b @Rm+,Rn
(Rm) -> sign extension -> Rn, Rm+1 -> Rm
0110nnnnmmmm0100
LS LS
1 1 1 1 1 1
1 1 1 1/2 1 2
SH1 SH2 SH3 SH4 SH4A SH2A
mov.w @Rm+,Rn
(Rm) -> sign extension -> Rn, Rm+2 -> Rm
0110nnnnmmmm0101
LS LS
1 1 1 1 1 1
1 1 1 1/2 1 2
SH1 SH2 SH3 SH4 SH4A SH2A
mov.l @Rm+,Rn
(Rm) -> Rn, Rm+4 -> Rm
0110nnnnmmmm0110
LS LS
1 1 1 1 1 1
1 1 1 1/2 1 2
SH1 SH2 SH3 SH4 SH4A SH2A
mov.b Rm,@-Rn
Rn-1 -> Rn, Rm -> (Rn)
0010nnnnmmmm0100
LS LS
1 1 1 1 1 1
1 1 1 1/1 1 1
SH1 SH2 SH3 SH4 SH4A SH2A
mov.w Rm,@-Rn
Rn-2 -> Rn, Rm -> (Rn)
0010nnnnmmmm0101
LS LS
1 1 1 1 1 1
1 1 1 1/1 1 1
SH1 SH2 SH3 SH4 SH4A SH2A
mov.l Rm,@-Rn
Rn-4 -> Rn, Rm -> (Rn)
0010nnnnmmmm0110
LS LS
1 1 1 1 1 1
1 1 1 1/1 1 1
SH2A
mov.b @-Rm,R0
Rm-1 -> Rm, (Rm) -> sign extension -> R0
0100mmmm11001011
1
2
SH2A
mov.w @-Rm,R0
Rm-2 -> Rm, (Rm) -> sign extension -> R0
0100mmmm11011011
1
2
SH2A
mov.l @-Rm,R0
Rm-4 -> Rm, (Rm) -> R0
0100mmmm11101011
1
2
SH2A
mov.b R0,@Rn+
R0 -> (Rn), Rn+1 -> Rn
0100nnnn10001011
1
1
SH2A
mov.w R0,@Rn+
R0 -> (Rn), Rn+2 -> Rn
0100nnnn10011011
1
1
SH2A
mov.l R0,@Rn+
R0 -> (Rn), Rn+4 -> Rn
0100nnnn10101011
1
1
SH1 SH2 SH3 SH4 SH4A SH2A
mov.b @(disp,Rm),R0
(disp + Rm) -> sign extension -> R0
10000100mmmmdddd
LS LS
1 1 1 1 1 1
1 1 1 2 1 2
SH2A
mov.b @(disp12,Rm),Rn
(disp + Rm) -> sign extension -> Rn
0011nnnnmmmm0001 0100dddddddddddd
1
2
SH2A
movu.b @(disp12,Rm),Rn
(disp + Rm) -> zero extension -> Rn
0011nnnnmmmm0001 1000dddddddddddd
1
2
SH1 SH2 SH3 SH4 SH4A SH2A
mov.w @(disp,Rm),R0
(disp*2 + Rm) -> sign extension -> R0
10000101mmmmdddd
LS LS
1 1 1 1 1 1
1 1 1 2 1 2
SH2A
mov.w @(disp12,Rm),Rn
(disp*2 + Rm) -> sign extension -> Rn
0011nnnnmmmm0001 0101dddddddddddd
1
2
SH2A
movu.w @(disp12,Rm),Rn
(disp*2 + Rm) -> zero extension -> Rn
0011nnnnmmmm0001 1001dddddddddddd
1
2
SH1 SH2 SH3 SH4 SH4A SH2A
mov.l @(disp,Rm),Rn
(disp*4 + Rm) -> Rn
0101nnnnmmmmdddd
LS LS
1 1 1 1 1 1
1 1 1 2 1 2
SH2A
mov.l @(disp12,Rm),Rn
(disp*4 + Rm) -> Rn
0011nnnnmmmm0001 0110dddddddddddd
1
2
SH1 SH2 SH3 SH4 SH4A SH2A
mov.b R0,@(disp,Rn)
R0 -> (disp + Rn)
10000000nnnndddd
LS LS
1 1 1 1 1 1
1 1 1 1 1 0
SH2A
mov.b Rm,@(disp12,Rn)
Rm -> (disp + Rn)
0011nnnnmmmm0001 0000dddddddddddd
1
0
SH1 SH2 SH3 SH4 SH4A SH2A
mov.w R0,@(disp,Rn)
R0 -> (disp*2 + Rn)
10000001nnnndddd
LS LS
1 1 1 1 1 1
1 1 1 1 1 0
SH2A
mov.w Rm,@(disp12,Rn)
Rm -> (disp*2 + Rn)
0011nnnnmmmm0001 0001dddddddddddd
1
0
SH1 SH2 SH3 SH4 SH4A SH2A
mov.l Rm,@(disp,Rn)
Rm -> (disp*4 + Rn)
0001nnnnmmmmdddd
LS LS
1 1 1 1 1 1
1 1 1 1 1 0
SH2A
mov.l Rm,@(disp12,Rn)
Rm -> (disp*4 + Rn)
0011nnnnmmmm0001 0010dddddddddddd
1
0
SH1 SH2 SH3 SH4 SH4A SH2A
mov.b @(R0,Rm),Rn
(R0 + Rm) -> sign extension -> Rn
0000nnnnmmmm1100
LS LS
1 1 1 1 1 1
1 1 1 2 1 2
SH1 SH2 SH3 SH4 SH4A SH2A
mov.w @(R0,Rm),Rn
(R0 + Rm) -> sign extension -> Rn
0000nnnnmmmm1101
LS LS
1 1 1 1 1 1
1 1 1 2 1 2
SH1 SH2 SH3 SH4 SH4A SH2A
mov.l @(R0,Rm),Rn
(R0 + Rm) -> Rn
0000nnnnmmmm1110
LS LS
1 1 1 1 1 1
1 1 1 2 1 2
SH1 SH2 SH3 SH4 SH4A SH2A
mov.b Rm,@(R0,Rn)
Rm -> (R0 + Rn)
0000nnnnmmmm0100
LS LS
1 1 1 1 1 1
1 1 1 1 1 0
SH1 SH2 SH3 SH4 SH4A SH2A
mov.w Rm,@(R0,Rn)
Rm -> (R0 + Rn)
0000nnnnmmmm0101
LS LS
1 1 1 1 1 1
1 1 1 1 1 0
SH1 SH2 SH3 SH4 SH4A SH2A
mov.l Rm,@(R0,Rn)
Rm -> (R0 + Rn)
0000nnnnmmmm0110
LS LS
1 1 1 1 1 1
1 1 1 1 1 0
SH1 SH2 SH3 SH4 SH4A SH2A
mov.b @(disp,GBR),R0
(disp + GBR) -> sign extension -> R0
11000100dddddddd
LS LS
1 1 1 1 1 1
1 1 1 2 1 2
SH1 SH2 SH3 SH4 SH4A SH2A
mov.w @(disp,GBR),R0
(disp*2 + GBR) -> sign extension -> R0
11000101dddddddd
LS LS
1 1 1 1 1 1
1 1 1 2 1 2
SH1 SH2 SH3 SH4 SH4A SH2A
mov.l @(disp,GBR),R0
(disp*4 + GBR) -> R0
11000110dddddddd
LS LS
1 1 1 1 1 1
1 1 1 2 1 2
SH1 SH2 SH3 SH4 SH4A SH2A
mov.b R0,@(disp,GBR)
R0 -> (disp + GBR)
11000000dddddddd
LS LS
1 1 1 1 1 1
1 1 1 1 1 0
SH1 SH2 SH3 SH4 SH4A SH2A
mov.w R0,@(disp,GBR)
R0 -> (disp*2 + GBR)
11000001dddddddd
LS LS
1 1 1 1 1 1
1 1 1 1 1 0
SH1 SH2 SH3 SH4 SH4A SH2A
mov.l R0,@(disp,GBR)
R0 -> (disp*4 + GBR)
11000010dddddddd
LS LS
1 1 1 1 1 1
1 1 1 1 1 0
SH4A
movco.l R0,@Rn
LDST -> T If (T == 1): R0 -> Rn 0 -> LDST
0000nnnn01110011
LDST
CO
1
1
SH4A
movli.l @Rm,R0
1 -> LDST (Rm) -> R0 When interrupt/exception occured: 0 -> LDST
0000mmmm01100011
CO
1
1
SH4A
movua.l @Rm,R0
(Rm) -> R0 Load non-boundary alignment data
0100mmmm10101001
LS
2
2
SH4A
movua.l @Rm+,R0
(Rm) -> R0, Rm + 4 -> Rm Load non-boundary alignment data
0100mmmm11101001
LS
2
2
SH2A
movml.l Rm,@-R15
R15-4 -> R15, Rm -> (R15) R15-4 -> R15, Rm-1 -> (R15) ... ... R15 - 4 -> R15, R0 -> (R15) Note: When Rm = R15, read Rm as PR
0100mmmm11110001
1-16
1-16
SH2A
movml.l @R15+,Rn
(R15) -> R0, R15+4 -> R15 (R15) -> R1, R15+4 -> R15 ... ... (R15) -> Rn Note: When Rn = R15, read Rn as PR
0100nnnn11110101
1-16
2-17
SH2A
movmu.l Rm,@-R15
R15-4 -> R15, PR -> (R15) R15-4 -> R15, R14 -> (R15) ... ... R15-4 -> R15, Rm -> (R15) Note: When Rm = R15, read Rm as PR
0100mmmm11110000
1-16
1-16
SH2A
movmu.l @R15+,Rn
(R15) -> Rn, R15+4 -> R15 (R15) -> Rn+1, R15+4 -> R15 ... ... (R15) -> R14, R15+4 -> R15 (R15) -> PR Note: When Rn = R15, read Rn as PR
0100nnnn11110100
1-16
2-17
SH2A
movrt Rn
~T -> Rn
0000nnnn00111001
1
1
SH1 SH2 SH3 SH4 SH4A SH2A
movt Rn
T -> Rn
0000nnnn00101001
EX EX
1 1 1 1 1 1
1 1 1 1 1 1
SH2A
nott
~T -> T
0000000001101000
~T
1
1
SH1 SH2 SH3 SH4 SH4A SH2A
swap.b Rm,Rn
Rm -> swap lower 2 bytes -> Rn
0110nnnnmmmm1000
EX EX
1 1 1 1 1 1
1 1 1 1 1 1
SH1 SH2 SH3 SH4 SH4A SH2A
swap.w Rm,Rn
Rm -> swap upper/lower words -> Rn
0110nnnnmmmm1001
EX EX
1 1 1 1 1 1
1 1 1 1 1 1
SH1 SH2 SH3 SH4 SH4A SH2A
xtrct Rm,Rn
Rm:Rn middle 32 bits -> Rn
0010nnnnmmmm1101
EX EX
1 1 1 1 1 1
1 1 1 1 1 1

Bit Manipulation Instructions

SH2A
band.b #imm3,@disp12,Rn
(imm of (disp+Rn)) & T -> T
0011nnnn0iii1001 0100dddddddddddd
Result
3
3
SH2A
bandnot.b #imm3,@(disp12,Rn)
~(imm of (disp+Rn)) & T -> T
0011nnnn0iii1001 1100dddddddddddd
Result
3
3
SH2A
bclr.b #imm3,@(disp12,Rn)
0 -> (imm of (disp+Rn))
0011nnnn0iii1001 0000dddddddddddd
3
2
SH2A
bclr #imm3,Rn
0 -> imm of Rn
10000110nnnn0iii
1
1
SH2A
bld.b #imm3,@(disp12,Rn)
(imm of (disp+Rn)) -> T
0011nnnn0iii1001 0011dddddddddddd
Result
3
3
SH2A
bld #imm3,Rn
imm of Rn -> T
10000111nnnn1iii
Result
1
1
SH2A
bldnot.b #imm3,@(disp12,Rn)
~(imm of (disp+Rn)) -> T
0011nnnn0iii1001 1011dddddddddddd
Result
3
3
SH2A
bor.b #imm3,@(disp12,Rn)
(imm of (disp+Rn)) | T -> T
0011nnnn0iii1001 0101dddddddddddd
Result
3
3
SH2A
bornot.b #imm3,@(disp12,Rn)
~(imm of (disp+Rn)) | T -> T
0011nnnn0iii1001 1101dddddddddddd
Result
3
3
SH2A
bset.b #imm3,@(disp12,Rn)
1 -> (imm of (disp+Rn))
0011nnnn0iii1001 0001dddddddddddd
3
2
SH2A
bset #imm3,Rn
1 -> imm of Rn
10000110nnnn1iii
1
1
SH2A
bst.b #imm3,@(disp12,Rn)
T -> (imm of (disp+Rn))
0011nnnn0iii1001 0010dddddddddddd
3
2
SH2A
bst #imm3,Rn
T -> imm of Rn
10000111nnnn0iii
1
1
SH2A
bxor.b #imm3,@(disp12,Rn)
(imm of (disp+Rn)) ^ T -> T
0011nnnn0iii1001 0110dddddddddddd
Result
3
3

Arithmetic Operation Instructions

SH1 SH2 SH3 SH4 SH4A SH2A
add Rm,Rn
Rn + Rm -> Rn
0011nnnnmmmm1100
EX EX
1 1 1 1 1 1
1 1 1 1 1 1
SH1 SH2 SH3 SH4 SH4A SH2A
add #imm,Rn
Rn + (sign extension)imm
0111nnnniiiiiiii
EX EX
1 1 1 1 1 1
1 1 1 1 1 1
SH1 SH2 SH3 SH4 SH4A SH2A
addc Rm,Rn
Rn + Rm + T -> Rn, carry -> T
0011nnnnmmmm1110
Carry
EX EX
1 1 1 1 1 1
1 1 1 1 1 1
SH1 SH2 SH3 SH4 SH4A SH2A
addv Rm,Rn
Rn + Rm -> Rn, overflow -> T
0011nnnnmmmm1111
Overflow
EX EX
1 1 1 1 1 1
1 1 1 1 1 1
SH1 SH2 SH3 SH4 SH4A SH2A
cmp/eq #imm,R0
If R0 = (sign extension)imm: 1 -> T Else: 0 -> T
10001000iiiiiiii
Result
MT EX
1 1 1 1 1 1
1 1 1 1 1 1
SH1 SH2 SH3 SH4 SH4A SH2A
cmp/eq Rm,Rn
If Rn = Rm: 1 -> T Else: 0 -> T
0011nnnnmmmm0000
Result
MT EX
1 1 1 1 1 1
1 1 1 1 1 1
SH1 SH2 SH3 SH4 SH4A SH2A
cmp/hs Rm,Rn
If Rn >= Rm (unsigned): 1 -> T Else: 0 -> T
0011nnnnmmmm0010
Result
MT EX
1 1 1 1 1 1
1 1 1 1 1 1
SH1 SH2 SH3 SH4 SH4A SH2A
cmp/ge Rm,Rn
If Rn >= Rm (signed): 1 -> T Else: 0 -> T
0011nnnnmmmm0011
Result
MT EX
1 1 1 1 1 1
1 1 1 1 1 1
SH1 SH2 SH3 SH4 SH4A SH2A
cmp/hi Rm,Rn
If Rn > Rm (unsigned): 1 -> T Else: 0 -> T
0011nnnnmmmm0110
Result
MT EX
1 1 1 1 1 1
1 1 1 1 1 1
SH1 SH2 SH3 SH4 SH4A SH2A
cmp/gt Rm,Rn
If Rn > Rm (signed): 1 -> T Else: 0 -> T
0011nnnnmmmm0111
Result
MT EX
1 1 1 1 1 1
1 1 1 1 1 1
SH1 SH2 SH3 SH4 SH4A SH2A
cmp/pl Rn
If Rn > 0 (signed): 1 -> T Else: 0 -> T
0100nnnn00010101
Result
MT EX
1 1 1 1 1 1
1 1 1 1 1 1
SH1 SH2 SH3 SH4 SH4A SH2A
cmp/pz Rn
If Rn >= 0 (signed): 1 -> T Else: 0 -> T
0100nnnn00010001
Result
MT EX
1 1 1 1 1 1
1 1 1 1 1 1
SH1 SH2 SH3 SH4 SH4A SH2A
cmp/str Rm,Rn
If Rn and Rm have an equal byte: 1 -> T Else: 0 -> T
0010nnnnmmmm1100
Result
MT EX
1 1 1 1 1 1
1 1 1 1 1 1
SH2A
clips.b Rn
If Rn > 0x0000007F: 0x0000007F -> Rn, 1 -> CS If Rn < 0xFFFFFF80: 0xFFFFFF80 -> Rn, 1 -> CS
0100nnnn10010001
1
1
SH2A
clips.w Rn
If Rn > 0x00007FFF: 0x00007FFF -> Rn, 1 -> CS If Rn < 0xFFFF8000: 0xFFFF8000 -> Rn, 1 -> CS
0100nnnn10010101
1
1
SH2A
clipu.b Rn
If Rn > 0x000000FF: 0x000000FF -> Rn, 1 -> CS
0100nnnn10000001
1
1
SH2A
clipu.w Rn
If Rn > 0x0000FFFF: 0x0000FFFF -> Rn, 1 -> CS
0100nnnn10000101
1
1
SH1 SH2 SH3 SH4 SH4A SH2A
div0s Rm,Rn
MSB of Rn -> Q, MSB of Rm -> M, M ^ Q -> T
0010nnnnmmmm0111
Result
EX EX
1 1 1 1 1 1
1 1 1 1 1 1
SH1 SH2 SH3 SH4 SH4A SH2A
div0u
0 -> M, 0 -> Q, 0 -> T
0000000000011001
0
EX EX
1 1 1 1 1 1
1 1 1 1 1 1
SH1 SH2 SH3 SH4 SH4A SH2A
div1 Rm,Rn
1-step division (Rn / Rm)
0011nnnnmmmm0100
Result
EX EX
1 1 1 1 1 1
1 1 1 1 1 1
SH2A
divs R0,Rn
Signed, Rn / R0 -> Rn 32 / 32 -> 32 bits
0100nnnn10010100
36
36
SH2A
divu R0,Rn
Unsigned, Rn / R0 -> Rn 32 / 32 -> 32 bits
0100nnnn10000100
36
36
SH2 SH3 SH4 SH4A SH2A
dmuls.l Rm,Rn
Signed, Rn * Rm -> MACH:MACL 32 * 32 -> 64 bits
0011nnnnmmmm1101
CO EX
2 2 2 1 2
2-4 2-5 4/4 2 3
SH2 SH3 SH4 SH4A SH2A
dmulu.l Rm,Rn
Unsigned, Rn * Rm -> MACH:MACL 32 * 32 -> 64 bits
0011nnnnmmmm0101
CO EX
2 2 2 1 2
2-4 2-5 4/4 2 2
SH2 SH3 SH4 SH4A SH2A
dt Rn
Rn-1 -> Rn If Rn = 0: 1 -> T Else: 0 -> T
0100nnnn00010000
EX EX
1 1 1 1 1
1 1 1 1 1
SH1 SH2 SH3 SH4 SH4A SH2A
exts.b Rm,Rn
Rm sign-extended from byte -> Rn
0110nnnnmmmm1110
EX EX
1 1 1 1 1 1
1 1 1 1 1 1
SH1 SH2 SH3 SH4 SH4A SH2A
exts.w Rm,Rn
Rm sign-extended from word -> Rn
0110nnnnmmmm1111
EX EX
1 1 1 1 1 1
1 1 1 1 1 1
SH1 SH2 SH3 SH4 SH4A SH2A
extu.b Rm,Rn
Rm zero-extended from byte -> Rn
0110nnnnmmmm1100
EX EX
1 1 1 1 1 1
1 1 1 1 1 1
SH1 SH2 SH3 SH4 SH4A SH2A
extu.w Rm,Rn
Rm zero-extended from word -> Rn
0110nnnnmmmm1101
EX EX
1 1 1 1 1 1
1 1 1 1 1 1
SH2 SH3 SH4 SH4A SH2A
mac.l @Rm+,@Rn+
Signed, (Rn) * (Rm) + MAC -> MAC 32 * 32 + 64 -> 64 bits
0000nnnnmmmm1111
CO CO
2 2 2 2 4
2-4 2-5 2/4 5 5
SH1 SH2 SH3 SH4 SH4A SH2A
mac.w @Rm+,@Rn+
Signed, (Rn) * (Rm) + MAC -> MAC SH1: 16 * 16 + 42 -> 42 bits Other: 16 * 16 + 64 -> 64 bits
0100nnnnmmmm1111
CO CO
2 2 2 2 2 3
2-3 2-3 2-5 2/4 4 4
SH2 SH3 SH4 SH4A SH2A
mul.l Rm,Rn
Rn * Rm -> MACL 32 * 32 -> 32 bits
0000nnnnmmmm0111
CO EX
2 2 2 1 2
2-4 2-4 4/4 2 3
SH2A
mulr R0,Rn
R0 * Rn -> Rn 32 * 32 -> 32 bits
0100nnnn10000000
2
4
SH1 SH2 SH3 SH4 SH4A SH2A
muls.w Rm,Rn
Signed, Rn * Rm -> MACL 16 * 16 -> 32 bits
0010nnnnmmmm1111
CO EX
2 2 2 2 1 1
1-3 1-3 1-3 4/4 1 2
SH1 SH2 SH3 SH4 SH4A SH2A
mulu.w Rm,Rn
Unsigned, Rn * Rm -> MACL 16 * 16 -> 32 bits
0010nnnnmmmm1110
CO EX
2 2 2 2 1 1
1-3 1-3 1-3 4/4 1 2
SH1 SH2 SH3 SH4 SH4A SH2A
neg Rm,Rn
0 - Rm -> Rn
0110nnnnmmmm1011
EX EX
1 1 1 1 1 1
1 1 1 1 1 1
SH1 SH2 SH3 SH4 SH4A SH2A
negc Rm,Rn
0 - Rm - T -> Rn, borrow -> T
0110nnnnmmmm1010
Borrow
EX EX
1 1 1 1 1 1
1 1 1 1 1 1
SH1 SH2 SH3 SH4 SH4A SH2A
sub Rm,Rn
Rn - Rm -> Rn
0011nnnnmmmm1000
EX EX
1 1 1 1 1 1
1 1 1 1 1 1
SH1 SH2 SH3 SH4 SH4A SH2A
subc Rm,Rn
Rn - Rm - T -> Rn, borrow -> T
0011nnnnmmmm1010
Borrow
EX EX
1 1 1 1 1 1
1 1 1 1 1 1
SH1 SH2 SH3 SH4 SH4A SH2A
subv Rm,Rn
Rn - Rm -> Rn, underflow -> T
0011nnnnmmmm1011
Underflow
EX EX
1 1 1 1 1 1
1 1 1 1 1 1

Logic Operation Instructions

SH1 SH2 SH3 SH4 SH4A SH2A
and Rm,Rn
Rn & Rm -> Rn
0010nnnnmmmm1001
EX EX
1 1 1 1 1 1
1 1 1 1 1 1
SH1 SH2 SH3 SH4 SH4A SH2A
and #imm,R0
R0 & (zero extend)imm -> R0
11001001iiiiiiii
EX EX
1 1 1 1 1 1
1 1 1 1 1 1
SH1 SH2 SH3 SH4 SH4A SH2A
and.b #imm,@(R0,GBR)
(R0 + GBR) & (zero extend)imm -> (R0 + GBR)
11001101iiiiiiii
CO CO
2 2 2 4 3 3
3 3 3 4 3
SH1 SH2 SH3 SH4 SH4A SH2A
not Rm,Rn
~Rm -> Rn
0110nnnnmmmm0111
EX EX
1 1 1 1 1 1
1 1 1 1 1 1
SH1 SH2 SH3 SH4 SH4A SH2A
or Rm,Rn
Rn | Rm -> Rn
0010nnnnmmmm1011
EX EX
1 1 1 1 1 1
1 1 1 1 1 1
SH1 SH2 SH3 SH4 SH4A SH2A
or #imm,R0
R0 | (zero extend)imm -> R0
11001011iiiiiiii
EX EX
1 1 1 1 1 1
1 1 1 1 1 1
SH1 SH2 SH3 SH4 SH4A SH2A
or.b #imm,@(R0,GBR)
(R0 + GBR) | (zero extend)imm -> (R0 + GBR)
11001111iiiiiiii
CO CO
2 2 2 4 3 3
3 3 3 4 3 2
SH1 SH2 SH3 SH4 SH4A SH2A
tas.b @Rn
If (Rn) = 0: 1 -> T Else: 0 -> T 1 -> MSB of (Rn)
0100nnnn00011011
Result
CO CO
2 2 2 5 4 3
4 4 3/4 5 4 3
SH1 SH2 SH3 SH4 SH4A SH2A
tst Rm,Rn
If Rn & Rm = 0: 1 -> T Else: 0 -> T
0010nnnnmmmm1000
Result
MT EX
1 1 1 1 1 1
1 1 1 1 1 1
SH1 SH2 SH3 SH4 SH4A SH2A
tst #imm,R0
If R0 & (zero extend)imm = 0: 1 -> T Else: 0 -> T
11001000iiiiiiii
Result
MT EX
1 1 1 1 1 1
1 1 1 1 1 1
SH1 SH2 SH3 SH4 SH4A SH2A
tst.b #imm,@(R0,GBR)
If (R0 + GBR) & (zero extend)imm = 0: 1 -> T Else 0: -> T
11001100iiiiiiii
Result
CO CO
2 2 2 3 3 3
3 3 3 3 3 3
SH1 SH2 SH3 SH4 SH4A SH2A
xor Rm,Rn
Rn ^ Rm -> Rn
0010nnnnmmmm1010
EX EX
1 1 1 1 1 1
1 1 1 1 1 1
SH1 SH2 SH3 SH4 SH4A SH2A
xor #imm,R0
R0 ^ (zero extend)imm -> R0
11001010iiiiiiii
EX EX
1 1 1 1 1 1
1 1 1 1 1 1
SH1 SH2 SH3 SH4 SH4A SH2A
xor.b #imm,@(R0,GBR)
(R0 + GBR) ^ (zero extend)imm -> (R0 + GBR)
11001110iiiiiiii
CO CO
2 2 2 4 3 3
3 3 3 4 3 2

Shift Instructions

SH1 SH2 SH3 SH4 SH4A SH2A
rotcl Rn
T << Rn << T
0100nnnn00100100
MSB
EX EX
1 1 1 1 1 1
1 1 1 1 1 1
SH1 SH2 SH3 SH4 SH4A SH2A
rotcr Rn
T >> Rn >> T
0100nnnn00100101
LSB
EX EX
1 1 1 1 1 1
1 1 1 1 1 1
SH1 SH2 SH3 SH4 SH4A SH2A
rotl Rn
T << Rn << MSB
0100nnnn00000100
MSB
EX EX
1 1 1 1 1 1
1 1 1 1 1 1
SH1 SH2 SH3 SH4 SH4A SH2A
rotr Rn
LSB >> Rn >> T
0100nnnn00000101
LSB
EX EX
1 1 1 1 1 1
1 1 1 1 1 1
SH3 SH4 SH4A SH2A
shad Rm,Rn
If Rm >= 0: Rn << Rm -> Rn If Rm < 0: Rn >> |Rm| -> [MSB -> Rn]
0100nnnnmmmm1100
EX EX
1 1 1 1
1 1 1 1
SH1 SH2 SH3 SH4 SH4A SH2A
shal Rn
T << Rn << 0
0100nnnn00100000
MSB
EX EX
1 1 1 1 1 1
1 1 1 1 1 1
SH1 SH2 SH3 SH4 SH4A SH2A
shar Rn
MSB >> Rn >> T
0100nnnn00100001
LSB
EX EX
1 1 1 1 1 1
1 1 1 1 1 1
SH3 SH4 SH4A SH2A
shld Rm,Rn
If Rm >= 0: Rn << Rm -> Rn If Rm < 0: Rn >> |Rm| -> [0 -> Rn]
0100nnnnmmmm1101
EX EX
1 1 1 1
1 1 1 1
SH1 SH2 SH3 SH4 SH4A SH2A
shll Rn
T << Rn << 0
0100nnnn00000000
MSB
EX EX
1 1 1 1 1 1
1 1 1 1 1 1
SH1 SH2 SH3 SH4 SH4A SH2A
shll2 Rn
Rn << 2 -> Rn
0100nnnn00001000
EX EX
1 1 1 1 1 1
1 1 1 1 1 1
SH1 SH2 SH3 SH4 SH4A SH2A
shll8 Rn
Rn << 8 -> Rn
0100nnnn00011000
EX EX
1 1 1 1 1 1
1 1 1 1 1 1
SH1 SH2 SH3 SH4 SH4A SH2A
shll16 Rn
Rn << 16 -> Rn
0100nnnn00101000
EX EX
1 1 1 1 1 1
1 1 1 1 1 1
SH1 SH2 SH3 SH4 SH4A SH2A
shlr Rn
0 >> Rn >> T
0100nnnn00000001
LSB
EX EX
1 1 1 1 1 1
1 1 1 1 1 1
SH1 SH2 SH3 SH4 SH4A SH2A
shlr2 Rn
Rn >> 2 -> [0 -> Rn]
0100nnnn00001001
EX EX
1 1 1 1 1 1
1 1 1 1 1 1
SH1 SH2 SH3 SH4 SH4A SH2A
shlr8 Rn
Rn >> 8 -> [0 -> Rn]
0100nnnn00011001
EX EX
1 1 1 1 1 1
1 1 1 1 1 1
SH1 SH2 SH3 SH4 SH4A SH2A
shlr16 Rn
Rn >> 16 -> [0 -> Rn]
0100nnnn00101001
EX EX
1 1 1 1 1 1
1 1 1 1 1 1

Branch Instructions

SH1 SH2 SH3 SH4 SH4A SH2A
bf label
If T = 0: disp*2 + PC + 4 -> PC Else: nop
10001011dddddddd
BR BR
1 1 1 1 1-3 1/3
1/3 1/3 1/3 1/2 1 1/3
SH2 SH3 SH4 SH4A SH2A
bf/s label
If T = 0: disp*2 + PC + 4 -> PC Else: nop (Delayed branch)
10001111dddddddd
BR BR
1 1 1 1-3 1/2
1/2 1/2 1/2 1 1/2
SH1 SH2 SH3 SH4 SH4A SH2A
bt label
If T = 1: disp*2 + PC + 4 -> PC Else: nop
10001001dddddddd
BR BR
1 1 1 1 1-3 1/3
1/3 1/3 1/3 1/2 1 1/3
SH2 SH3 SH4 SH4A SH2A
bt/s label
If T = 1: disp*2 + PC + 4 -> PC Else: nop (Delayed branch)
10001101dddddddd
BR BR
1 1 1 1-3 1/2
1/2 1/2 1/2 1 1/2
SH1 SH2 SH3 SH4 SH4A SH2A
bra label
disp*2 + PC + 4 -> PC (Delayed branch)
1010dddddddddddd
BR BR
1 1 1 1 1-3 2
2 2 2 2 1 2
SH2 SH3 SH4 SH4A SH2A
braf Rm
Rm + PC + 4 -> PC (Delayed branch)
0000mmmm00100011
CO BR
1 1 2 4 2
2 2 3 1 2
SH1 SH2 SH3 SH4 SH4A SH2A
bsr label
PC + 4 -> PR, disp*2 + PC + 4 -> PC (Delayed branch)
1011dddddddddddd
BR BR
1 1 1 1 1-3 2
2 2 2 2 1 2
SH2 SH3 SH4 SH4A SH2A
bsrf Rm
PC + 4 -> PR, Rm + PC + 4 -> PC (Delayed branch)
0000mmmm00000011
CO BR
1 1 2 4 2
2 2 3 1 2
SH1 SH2 SH3 SH4 SH4A SH2A
jmp @Rm
Rm -> PC (Delayed branch)
0100mmmm00101011
CO BR
1 1 1 2 4 2
2 2 2 3 1 2
SH1 SH2 SH3 SH4 SH4A SH2A
jsr @Rm
PC + 4 -> PR, Rm -> PC (Delayed branch)
0100mmmm00001011
CO BR
1 1 1 2 4 2
2 2 2 3 1 2
SH2A
jsr/n @Rm
PC + 2 -> PR, Rm -> PC
0100mmmm01001011
3
3
SH2A
jsr/n @@(disp8,TBR)
PC + 2 -> PR, (disp*4 + TBR) -> PC
10000011dddddddd
5
5
SH1 SH2 SH3 SH4 SH4A SH2A
rts
PR -> PC Delayed branch
0000000000001011
CO BR
1 1 1 2 1-4 2
2 2 2 3 1 2
SH2A
rts/n
PR -> PC
0000000001101011
3
3
SH2A
rtv/n Rm
Rm -> R0, PR -> PC
0000mmmm01111011
3
3

System Control Instructions

SH1 SH2 SH3 SH4 SH4A SH2A
clrmac
0 -> MACH, 0 -> MACL
0000000000101000
CO EX
1 1 1 1 1 1
1 1 1 3 1 1
SH3 SH4 SH4A
clrs
0 -> S
0000000001001000
CO EX
1 1 1
1 1 1
SH1 SH2 SH3 SH4 SH4A SH2A
clrt
0 -> T
0000000000001000
0
MT EX
1 1 1 1 1 1
1 1 1 1 1 1
SH4A
icbi @Rn
Invalidate instruction cache block indicated by logical address
0000nnnn11100011
CO
16
13
SH2A
ldbank @Rm,R0
(Specified register bank entry) -> R0
0100mmmm11100101
6
5
SH1 SH2 SH3 SH4 SH4A SH2A Privileged
ldc Rm,SR
Rm -> SR
0100mmmm00001110
LSB
CO CO
1 1 1 4 7 3
1 1 5 4 4 2
SH1 SH2 SH3 SH4 SH4A SH2A Privileged
ldc.l @Rm+,SR
(Rm) -> SR, Rm+4 -> Rm
0100mmmm00000111
LSB
CO CO
1 1 2 4 9 5
3 3 7 4/4 4 4
SH2A
ldc Rm,TBR
Rm -> TBR
0100mmmm01001010
1
1
SH1 SH2 SH3 SH4 SH4A SH2A
ldc Rm,GBR
Rm -> GBR
0100mmmm00011110
CO LS
1 1 1 3 1 1
1 1 1/3 3 1 1
SH1 SH2 SH3 SH4 SH4A SH2A
ldc.l @Rm+,GBR
(Rm) -> GBR, Rm+4 -> Rm
0100mmmm00010111
CO LS
1 1 1 3 1 1
3 3 1/5 3/3 1 2
SH1 SH2 SH3 SH4 SH4A SH2A Privileged
ldc Rm,VBR
Rm -> VBR
0100mmmm00101110
CO LS
1 1 1 1 1 1
1 1 1/3 3 1 1
SH1 SH2 SH3 SH4 SH4A SH2A Privileged
ldc.l @Rm+,VBR
(Rm) -> VBR, Rm+4 -> Rm
0100mmmm00100111
CO LS
1 1 1 1 1 1
3 3 1/5 1/3 1 2
DSP
ldc Rm,MOD
Rm -> MOD
0100mmmm01011110
1
1/3
DSP
ldc.l @Rm+,MOD
(Rm) -> MOD, Rm+4 -> Rm
0100mmmm01010111
1
1/5
DSP
ldc Rm,RE
Rm -> RE
0100mmmm01111110
1
1/3
DSP
ldc.l @Rm+,RE
(Rm) -> RE, Rm+4 -> Rm
0100mmmm01110111
1
1/5
DSP
ldc Rm,RS
Rm -> RS
0100mmmm01101110
1
1/3
DSP
ldc.l @Rm+,RS
(Rm) -> RS, Rm+4 -> Rm
0100mmmm01100111
1
1/5
SH4A Privileged
ldc Rm,SGR
Rm -> SGR
0100mmmm00111010
CO
4
4
SH4A Privileged
ldc.l @Rm+,SGR
(Rm) -> SGR, Rm+4 -> Rm
0100mmmm00110110
CO
4
4
SH3 SH4 SH4A Privileged
ldc Rm,SSR
Rm -> SSR
0100mmmm00111110
CO LS
1 1 1
1/3 3 1
SH3 SH4 SH4A Privileged
ldc.l @Rm+,SSR
(Rm) -> SSR, Rm+4 -> Rm
0100mmmm00110111
CO LS
1 1 1
1/5 1/3 1
SH3 SH4 SH4A Privileged
ldc Rm,SPC
Rm -> SPC
0100mmmm01001110
CO LS
1 3 1
1/3 1 1
SH3 SH4 SH4A Privileged
ldc.l @Rm+,SPC
(Rm) -> SPC, Rm+4 -> Rm
0100mmmm01000111
CO LS
1 1 1
1/5 1/3 1
SH4 SH4A Privileged
ldc Rm,DBR
Rm -> DBR
0100mmmm11110110
CO CO
1 4
3 4
SH4 SH4A Privileged
ldc.l @Rm+,DBR
(Rm) -> DBR, Rm+4 -> Rm
0100mmmm11110110
CO CO
1 4
1/3 4
SH3 SH4 SH4A Privileged
ldc Rm,Rn_BANK
Rm -> Rn_BANK (n = 0-7)
0100mmmm1nnn1110
CO LS
1 1 1
1/3 3 1
SH3 SH4 SH4A Privileged
ldc.l @Rm+,Rn_BANK
(Rm) -> Rn_BANK, Rm+4 -> Rm
0100mmmm1nnn0111
CO LS
1 1 1
1/5 1/3 1
DSP
ldre @(disp,PC)
disp*2 + PC -> RE
10001110dddddddd
1
3
DSP
ldrs @(disp,PC)
disp*2 + PC -> RS
10001100dddddddd
1
3
SH1 SH2 SH3 SH4 SH4A SH2A
lds Rm,MACH
Rm -> MACH
0100mmmm00001010
CO LS
1 1 1 1 1 1
1 1 1 3 1 1
SH1 SH2 SH3 SH4 SH4A SH2A
lds.l @Rm+,MACH
(Rm) -> MACH, Rm+4 -> Rm
0100mmmm00000110
CO LS
1 1 1 1 1 1
1 1 1 1/3 1 2
SH1 SH2 SH3 SH4 SH4A SH2A
lds Rm,MACL
Rm -> MACL
0100mmmm00011010
CO LS
1 1 1 1 1 1
1 1 1 3 1 1
SH1 SH2 SH3 SH4 SH4A SH2A
lds.l @Rm+,MACL
(Rm) -> MACL, Rm+4 -> Rm
0100mmmm00010110
CO LS
1 1 1 1 1 1
1 1 1 1/3 1 2
SH1 SH2 SH3 SH4 SH4A SH2A
lds Rm,PR
Rm -> PR
0100mmmm00101010
CO LS
1 1 1 2 1 1
1 1 1 3 1 1
SH1 SH2 SH3 SH4 SH4A SH2A
lds.l @Rm+,PR
(Rm) -> PR, Rm+4 -> Rm
0100mmmm00100110
CO LS
1 1 1 2 1 1
1 1 1 2/3 1 2
DSP
lds Rm,DSR
Rm -> DSR
0100mmmm01101010
1
1
DSP
lds.l @Rm+,DSR
(Rm) -> DSR, Rm+4 -> Rm
0100mmmm01100110
1
1/5
DSP
lds Rm,A0
Rm -> A0
0100mmmm01110110
1
1
DSP
lds.l @Rm+,A0
(Rm) -> A0, Rm+4 -> Rm
0100mmmm01110110
1
1
DSP
lds Rm,X0
Rm -> X0
0100mmmm10001010
1
1
DSP
lds.l @Rm+,X0
(Rm) -> X0, Rm+4 -> Rm
0100nnnn10000110
1
1/5
DSP
lds Rm,X1
Rm -> X1
0100mmmm10011010
1
1
DSP
lds.l @Rm+,X1
(Rm) -> X1, Rm+4 -> Rm
0100nnnn10010110
1
1/5
DSP
lds Rm,Y0
Rm -> Y0
0100mmmm10101010
1
1
DSP
lds.l @Rm+,Y0
(Rm) -> Y0, Rm+4 -> Rm
0100nnnn10100110
1
1/5
DSP
lds Rm,Y1
Rm -> Y1
0100mmmm10111010
1
1
DSP
lds.l @Rm+,Y1
(Rm) -> Y1, Rm+4 -> Rm
0100nnnn10110110
1
1
SH3 SH4 SH4A Privileged
ldtbl
PTEH/PTEL -> TLB
0000000000111000
CO CO
1 1 1
1 1 1
SH4 SH4A
movca.l R0,@Rn
R0 -> (Rn) (without fetching cache block)
0000nnnn11000011
LS LS
1 1
3-7 1
SH1 SH2 SH3 SH4 SH4A SH2A
nop
No operation
0000000000001001
MT MT
1 1 1 1 1 1
1 1 1 0 1 0
SH4 SH4A
ocbi @Rn
Invalidate operand cache block
0000nnnn10010011
LS LS
1 1
1-2 1
SH4 SH4A
ocbp @Rn
Write back and invalidate operand cache block
0000nnnn10100011
LS LS
1 1
1-5 1
SH4 SH4A
ocbwb @Rn
Write back operand cache block
0000nnnn10110011
LS LS
1 1
1-5 1
SH3 SH4 SH4A SH2A
pref @Rn
(Rn) -> operand cache
0000nnnn10000011
LS LS
1 1 1 1
1/2 1 1 0
SH4A
prefi @Rn
Reads 32-byte instruction block into instruction cache
0000nnnn11010011
CO
13
10
SH2A
resbank
Bank -> R0 to R14, GBR, MACH, MACL, PR
0000000001011011
9/19
8/20
SH1 SH2 SH3 SH4 SH4A SH2A Privileged
rte
Delayed branch SH1*,SH2*: stack area -> PC/SR SH3*,SH4*: SSR/SPC -> SR/PC
0000000000101011
CO CO
1 1 1 5 5 6
4 4 4 5 4 5
DSP
setrc Rn
Rn[11:0] -> RC (SR[27:16])
0100mmmm00010100
1
3
DSP
setrc #imm
imm -> RC (SR[23:16]), 0 -> SR[27:24]
10000010iiiiiiii
1
3
SH3 SH4 SH4A
sets
1 -> T
0000000000011000
CO EX
1 1 1
1 1 1
SH1 SH2 SH3 SH4 SH4A SH2A
sett
1 -> T
0000000000011000
1
MT EX
1 1 1 1 1 1
1 1 1 1 1 0
SH1 SH2 SH3 SH4 SH4A SH2A Privileged
sleep
Sleep or standby
0000000000011011
CO CO
1 1 2 4 ud 5
3 3 4 4 ud 0
SH2A
stbank R0,@Rn
R0 -> (specified register bank entry)
0100nnnn11100001
7
6
SH1 SH2 SH3 SH4 SH4A SH2A Privileged
stc SR,Rn
SR -> Rn
0000nnnn00000010
CO CO
1 1 1 2 1 2
1 1 1 2 1 2
SH1 SH2 SH3 SH4 SH4A SH2A Privileged
stc.l SR,@-Rn
Rn-4 -> Rn, SR -> (Rn)
0100nnnn00000011
CO CO
1 1 1 2 1 2
2 2 1/2 2/2 1 2
SH2A
stc TBR,Rn
TBR -> Rn
0000nnnn01001010
1
1
SH1 SH2 SH3 SH4 SH4A SH2A
stc GBR,Rn
GBR -> Rn
0000nnnn00010010
CO LS
1 1 1 2 1 1
1 1 1 2 1 1
SH1 SH2 SH3 SH4 SH4A SH2A
stc.l GBR,@-Rn
Rn-4 -> Rn, GBR -> (Rn)
0100nnnn00010011
CO LS
1 1 1 2 1 1
2 2 1/2 2/2 1 1
SH1 SH2 SH3 SH4 SH4A SH2A Privileged
stc VBR,Rn
VBR -> Rn
0000nnnn00100010
CO LS
1 1 1 2 1 1
1 1 1 2 1 1
SH1 SH2 SH3 SH4 SH4A SH2A Privileged
stc.l VBR,@-Rn
Rn-4 -> Rn, VBR -> (Rn)
0100nnnn00100011
CO LS
1 1 1 2 1 1
2 2 1/2 2/2 1 1
DSP
stc MOD,Rn
MOD -> Rn
0000nnnn01010010
1
1
DSP
stc.l MOD,@-Rn
Rn-4 -> Rn, MOD -> (Rn)
0100nnnn01010011
1
1/2
DSP
stc RE,Rn
RE -> Rn
0000nnnn01110010
1
1
DSP
stc.l RE,@-Rn
Rn-4 -> Rn, RE -> (Rn)
0100nnnn01110011
1
1/2
DSP
stc RS,Rn
RS -> Rn
0000nnnn01100010
1
1
DSP
stc.l RS,@-Rn
Rn-4 -> Rn, RS -> (Rn)
0100nnnn01100011
1
1/2
SH4 SH4A Privileged
stc SGR,Rn
SGR -> Rn
0000nnnn00111010
CO LS
3 1
3 1
SH4 SH4A Privileged
stc.l SGR,@-Rn
Rn-4 -> Rn, SGR -> (Rn)
0100nnnn00110010
CO LS
3 1
3/3 1
SH3 SH4 SH4A Privileged
stc SSR,Rn
SSR -> Rn
0000nnnn00110010
CO LS
1 2 1
1 2 1
SH3 SH4 SH4A Privileged
stc.l SSR,@-Rn
Rn-4 -> Rn, SSR -> (Rn)
0100nnnn00110011
CO LS
1 2 1
1/2 2 1
SH3 SH4 SH4A Privileged
stc SPC,Rn
SPC -> Rn
0000nnnn01000010
CO LS
1 2 1
1 2 1
SH3 SH4 SH4A Privileged
stc.l SPC,@-Rn
Rn-4 -> Rn, SPC -> (Rn)
0100nnnn01000011
CO LS
2 1
2/2 1
SH4 SH4A Privileged
stc DBR,Rn
DBR -> Rn
0000nnnn11111010
CO LS
2 1
2 1
SH4 SH4A Privileged
stc.l DBR,@-Rn
Rn-4 -> Rn, DBR -> (Rn)
0100nnnn11110010
CO LS
2 1
2/2 1
SH3 SH4 SH4A Privileged
stc Rm_BANK,Rn
Rm_BANK -> Rn (m = 0-7)
0000nnnn1mmm0010
CO LS
1 2 1
1 2 1
SH3 SH4 SH4A Privileged
stc.l Rm_BANK,@-Rn
Rn-4 -> Rn, Rm_BANK -> (Rn) (m = 0-7)
0100nnnn1mmm0011
CO LS
2 2 1
2 2/2 1
SH1 SH2 SH3 SH4 SH4A SH2A
sts MACH,Rn
MACH -> Rn
0000nnnn00001010
CO LS
1 1 1 1 1 1
1 1 1 3 1 2
SH1 SH2 SH3 SH4 SH4A SH2A
sts.l MACH,@-Rn
Rn-4 -> Rn, MACH -> (Rn)
0100nnnn00000010
CO LS
1 1 1 1 1 1
1 1 1 1/1 1 1
SH1 SH2 SH3 SH4 SH4A SH2A
sts MACL,Rn
MACL -> Rn
0000nnnn00011010
CO LS
1 1 1 1 1 1
1 1 1 3 1 2
SH1 SH2 SH3 SH4 SH4A SH2A
sts.l MACL,@-Rn
Rn-4 -> Rn, MACL -> (Rn)
0100nnnn00010010
CO LS
1 1 1 1 1 1
1 1 1 1/1 1 1
SH1 SH2 SH3 SH4 SH4A SH2A
sts PR,Rn
PR -> Rn
0000nnnn00101010
CO LS
1 1 1 2 1 1
1 1 1 2 1 1
SH1 SH2 SH3 SH4 SH4A SH2A
sts.l PR,@-Rn
Rn-4 -> Rn, PR -> (Rn)
0100nnnn00100010
CO LS
1 1 1 2 1 1
1 1 1 2/2 1 1
DSP
sts DSR,Rn
DSR -> Rn
0000nnnn01101010
1
1
DSP
sts.l DSR,@-Rn
Rn-4 -> Rn, DSR -> (Rn)
0100nnnn01100010
1
1
DSP
sts A0,Rn
A0 -> Rn
0000nnnn01111010
1
1
DSP
sts.l A0,@-Rn
Rn-4 -> Rn, A0 -> (Rn)
0100nnnn01100010
1
1
DSP
sts X0,Rn
X0 -> Rn
0000nnnn10001010
1
1
DSP
sts.l X0,@-Rn
Rn-4 -> Rn, X0 -> (Rn)
0100nnnn10000010
1
1
DSP
sts X1,Rn
X1 -> Rn
0000nnnn10011010
1
1
DSP
sts.l X1,@-Rn
Rn-4 -> Rn, X1 -> (Rn)
0100nnnn10010010
1
1
DSP
sts Y0,Rn
Y0 -> Rn
0000nnnn10101010
1
1
DSP
sts.l Y0,@-Rn
Rn-4 -> Rn, Y0 -> (Rn)
0100nnnn10100010
1
1
DSP
sts Y1,Rn
Y1 -> Rn
0000nnnn10111010
1
1
DSP
sts.l Y1,@-Rn
Rn-4 -> Rn, Y1 -> (Rn)
0100nnnn10110010
1
1
SH4A
synco
Prevents the next instruction from being issued until instructions issued before this instruction has been completed.
0000000010101011
CO
ud
ud
SH1 SH2 SH3 SH4 SH4A SH2A
trapa #imm
SH1*,SH2*: PC/SR -> stack area, (imm*4 + VBR) -> PC SH3*,SH4*: PC/SR -> SPC/SSR, imm*4 -> TRA, 0x160 -> EXPEVT, VBR + 0x0100 -> PC
11000011iiiiiiii
CO CO
2 2 2 7 14 5
8 8 8 7 13 6

32 Bit Floating-Point Data Transfer Instructions (FPSCR.SZ = 0)

SH2E SH3E SH4 SH4A SH2A
fmov FRm,FRn
FRm -> FRn
1111nnnnmmmm1100
LS LS
1 1 1 1 1
1 1 0 1 0
SH2E SH3E SH4 SH4A SH2A
fmov.s @Rm,FRn
(Rm) -> FRn
1111nnnnmmmm1000
LS LS
1 1 1 1 1
1 1 2 1 0/2
SH2E SH3E SH4 SH4A SH2A
fmov.s FRm,@Rn
FRm -> (Rn)
1111nnnnmmmm1010
LS LS
1 1 1 1 1
1 1 1 1 0
SH2E SH3E SH4 SH4A SH2A
fmov.s @Rm+,FRn
(Rm) -> FRn, Rm+4 -> Rm
1111nnnnmmmm1001
LS LS
1 1 1 1 1
1 1 1/2 1 1/2
SH2E SH3E SH4 SH4A SH2A
fmov.s FRm,@-Rn
Rn-4 -> Rn, FRm -> (Rn)
1111nnnnmmmm1011
LS LS
1 1 1 1 1
1 1 1/1 1 1/0
SH2E SH3E SH4 SH4A SH2A
fmov.s @(R0,Rm),FRn
(R0 + Rm) -> FRn
1111nnnnmmmm0110
LS LS
1 1 1 1 1
1 1 2 1 0/2
SH2E SH3E SH4 SH4A SH2A
fmov.s FRm,@(R0,Rn)
FRm -> (R0 + Rn)
1111nnnnmmmm0111
LS LS
1 1 1 1 1
1 1 1 1 0
SH2A
fmov.s @(disp12,Rm),FRn
(disp*4 + Rm) -> FRn
0011nnnnmmmm0001 0111dddddddddddd
1
0/2
SH2A
fmov.s FRm,@(disp12,Rn)
FRm -> (disp*4 + Rn)
0011nnnnmmmm0001 0011dddddddddddd
1
0

64 Bit Floating-Point Data Transfer Instructions (FPSCR.SZ = 1)

SH4 SH4A SH2A
fmov DRm,DRn
DRm -> DRn
1111nnn0mmm01100
LS LS
1 1 2
0 1 1
SH4 SH4A
fmov DRm,XDn
DRm -> XDn
1111nnn1mmm01100
LS LS
1 1
0 1
SH4 SH4A
fmov XDm,DRn
XDm -> DRn
1111nnn0mmm11100
LS LS
1 1
0 1
SH4 SH4A
fmov XDm,XDn
XDm -> XDn
1111nnn1mmm11100
LS LS
1 1
0 1
SH4 SH4A SH2A
fmov.d @Rm,DRn
(Rm) -> DRn
1111nnn0mmmm1000
LS LS
1 1 2
2 1 0/4
SH4 SH4A
fmov.d @Rm,XDn
(Rm) -> XDn
1111nnn1mmmm1000
LS LS
1 1
2 1
SH4 SH4A SH2A
fmov.d DRm,@Rn
DRm -> (Rn)
1111nnnnmmm01010
LS LS
1 1 2
1 1 0
SH4 SH4A
fmov.d XDm,@Rn
XDm -> (Rn)
1111nnnnmmm11010
LS LS
1 1
1 1
SH4 SH4A SH2A
fmov.d @Rm+,DRn
(Rm) -> DRn, Rm + 8 -> Rm
1111nnn0mmmm1001
LS LS
1 1 2
1/2 1 1/4
SH4 SH4A
fmov.d @Rm+,XDn
(Rm) -> XDn, Rm+8 -> Rm
1111nnn1mmmm1001
LS LS
1 1
1/2 1
SH4 SH4A SH2A
fmov.d DRm,@-Rn
Rn-8 -> Rn, DRm -> (Rn)
1111nnnnmmm01011
LS LS
1 1 2
1/1 1 0/1
SH4 SH4A
fmov.d XDm,@-Rn
Rn-8 -> Rn, (Rn) -> XDm
1111nnnnmmm11011
LS LS
1 1
1/1 1
SH4 SH4A SH2A
fmov.d @(R0,Rm),DRn
(R0 + Rm) -> DRn
1111nnn0mmmm0110
LS LS
1 1 2
2 1 0/4
SH4 SH4A
fmov.d @(R0,Rm),XDn
(R0 + Rm) -> XDn
1111nnn1mmmm0110
LS LS
1 1
2 1
SH4 SH4A SH2A
fmov.d DRm,@(R0,Rn)
DRm -> (R0 + Rn)
1111nnnnmmm00111
LS LS
1 1 2
1 1 0
SH4 SH4A
fmov.d XDm,@(R0,Rn)
XDm -> (R0 + Rn)
1111nnnnmmm10111
LS LS
1 1
1 1
SH2A
fmov.d @(disp12,Rm),DRn
(disp*8 + Rm) -> DRn
0011nnn0mmmm0001 0111dddddddddddd
2
0/4
SH2A
fmov.d DRm,@(disp12,Rn)
DRm -> (disp*8 + Rn)
0011nnnnmmm00001 0011dddddddddddd
2
0

Floating-Point Single-Precision Instructions (FPSCR.PR = 0)

SH2E SH3E SH4 SH4A SH2A
fldi0 FRn
0x00000000 -> FRn
1111nnnn10001101
LS LS
1 1 1 1 1
1 1 0 1 0
SH2E SH3E SH4 SH4A SH2A
fldi1 FRn
0x3F800000 -> FRn
1111nnnn10011101
LS LS
1 1 1 1 1
1 1 0 1 0
SH2E SH3E SH4 SH4A SH2A
flds FRm,FPUL
FRm -> FPUL
1111mmmm00011101
LS LS
1 1 1 1 1
1 1 0 1 0
SH2E SH3E SH4 SH4A SH2A
fsts FPUL,FRn
FPUL -> FRn
1111nnnn00001101
LS LS
1 1 1 1 1
1 1 0 1 0
SH2E SH3E SH4 SH4A SH2A
fabs FRn
FRn & 0x7FFFFFFF -> FRn
1111nnnn01011101
LS LS
1 1 1 1 1
1 1 0 1 0
SH2E SH3E SH4 SH4A SH2A
fneg FRn
FRn ^ 0x80000000 -> FRn
1111nnnn01001101
LS LS
1 1 1 1 1
1 1 0 1 0
SH2E SH3E SH4 SH4A SH2A
fadd FRm,FRn
FRn + FRm -> FRn
1111nnnnmmmm0000
FE FE
1 1 1 1 1
1 1 3/4 1 3
SH2E SH3E SH4 SH4A SH2A
fsub FRm,FRn
FRn - FRm -> FRn
1111nnnnmmmm0001
FE FE
1 1 1 1 1
1 1 3/4 1 3
SH2E SH3E SH4 SH4A SH2A
fmul FRm,FRn
FRn * FRm -> FRn
1111nnnnmmmm0010
FE FE
1 1 1 1 1
1 1 3/4 1 3
SH2E SH3E SH4 SH4A SH2A
fmac FR0,FRm,FRn
FR0 * FRm + FRn -> FRn
1111nnnnmmmm1110
FE FE
1 1 1 1 1
1 1 3/4 1 3
SH2E SH3E SH4 SH4A SH2A
fdiv FRm,FRn
FRn / FRm -> FRn
1111nnnnmmmm0011
FE FE
1 1 1 1 1
13 13 12/13 14 12
SH3E SH4 SH4A SH2A
fsqrt FRn
sqrt (FRn) -> FRn
1111nnnn01101101
FE FE
1 1 1 1
13 11/12 30 11
SH2E SH3E SH4 SH4A SH2A
fcmp/eq FRm,FRn
If FRn = FRm: 1 -> T Else: 0 -> T
1111nnnnmmmm0100
Result
FE FE
1 1 1 1 1
1 1 2/4 1 2
SH2E SH3E SH4 SH4A SH2A
fcmp/gt FRm,FRn
If FRn > FRm: 1 -> T Else: 0 -> T
1111nnnnmmmm0101
Result
FE FE
1 1 1 1 1
1 1 2/4 1 2
SH2E SH3E SH4 SH4A SH2A
float FPUL,FRn
(float)FPUL -> FRn
1111nnnn00101101
FE FE
1 1 1 1 1
1 1 3/4 1 3
SH2E SH3E SH4 SH4A SH2A
ftrc FRm,FPUL
(long)FRm -> FPUL
1111mmmm00111101
FE FE
1 1 1 1 1
1 1 3/4 1 3
SH4 SH4A
fipr FVm,FVn
inner_product (FVm, FVn) -> FR[n+3]
1111nnmm11101101
FE FE
1 1
4/5 1
SH4 SH4A
ftrv XMTRX,FVn
transform_vector (XMTRX, FVn) -> FVn
1111nn0111111101
FE FE
1 1
5/8 4
SH4A
fsrra FRn
1.0 / sqrt (FRn) -> FRn
1111nnnn01111101
FE
1
1
SH4A
fsca FPUL,DRn
sin (FPUL) -> FRn cos (FPUL) -> FR[n+1]
1111nnn011111101
FE
1
3

Floating-Point Double-Precision Instructions (FPSCR.PR = 1)

SH4 SH4A SH2A
fabs DRn
DRn & 0x7FFFFFFFFFFFFFFF -> DRn
1111nnn001011101
LS LS
1 1 1
0 1 0
SH4 SH4A SH2A
fneg DRn
DRn ^ 0x8000000000000000 -> DRn
1111nnn001001101
FS LS
1 1 1
0 1 0
SH4 SH4A SH2A
fadd DRm,DRn
DRn + DRm -> DRn
1111nnn0mmm00000
FE FE
1 1 1
7/9 1 0/8
SH4 SH4A SH2A
fsub DRm,DRn
DRn - DRm -> DRn
1111nnn0mmm00001
FE FE
1 1 1
7/9 1 0/8
SH4 SH4A SH2A
fmul DRm,DRn
DRn * DRm -> DRn
1111nnn0mmm00010
FE FE
1 1 1
7/9 3 0/8
SH4 SH4A SH2A
fdiv DRm,DRn
DRn / DRm -> DRn
1111nnn0mmm00011
FE FE
1 1 1
24/26 14 0/24
SH4 SH4A SH2A
fsqrt DRn
sqrt (DRn) -> DRn
1111nnn001101101
FE FE
1 1 1
23/25 30 0/24
SH4 SH4A SH2A
fcmp/eq DRm,DRn
If DRn = DRm: 1 -> T Else: 0 -> T
1111nnn0mmm00100
CO FE
2 1 2
3/5 1 3
SH4 SH4A SH2A
fcmp/gt DRm,DRn
If DRn > DRm: 1 -> T Else: 0 -> T
1111nnn0mmm00101
CO FE
2 1 2
3/5 1 3
SH4 SH4A SH2A
float FPUL,DRn
(double)FPUL -> DRn
1111nnn000101101
FE FE
1 1 1
3/5 1 0/4
SH4 SH4A SH2A
ftrc DRm,FPUL
(long)DRm -> FPUL
1111mmm000111101
FE FE
1 1 1
4/5 1 0/4
SH4 SH4A SH2A
fcnvds DRm,FPUL
double_to_float (DRm) -> FPUL
1111mmm010111101
FE FE
1 1 1
4/5 1 4
SH4 SH4A SH2A
fcnvsd FPUL,DRn
float_to_double (FPUL) -> DRn
1111nnn010101101
FE FE
1 1 1
3/5 1 4

Floating-Point Control Instructions

SH2E SH3E SH4 SH4A SH2A
lds Rm,FPSCR
Rm -> FPSCR
0100mmmm01101010
CO LS
1 1 1 1 1
1 1 4 1 3
SH2E SH3E SH4 SH4A SH2A
sts FPSCR,Rn
FPSCR -> Rn
0000nnnn01101010
CO LS
1 1 1 1 1
1 1 3 1 2
SH2E SH3E SH4 SH4A SH2A
lds.l @Rm+,FPSCR
(Rm) -> FPSCR, Rm+4 -> Rm
0100mmmm01100110
CO LS
1 1 1 1 1
1 1 3 1 3
SH2E SH3E SH4 SH4A SH2A
sts.l FPSCR,@-Rn
Rn-4 -> Rn, FPSCR -> (Rn)
0100nnnn01100010
CO LS
1 1 1 1 1
1 1 1/1 1 1
SH2E SH3E SH4 SH4A SH2A
lds Rm,FPUL
Rm -> FPUL
0100mmmm01011010
LS LS
1 1 1 1 1
1 1 1 1 1
SH2E SH3E SH4 SH4A SH2A
sts FPUL,Rn
FPUL -> Rn
0000nnnn01011010
LS LS
1 1 1 1 1
1 1 3 1 2
SH2E SH3E SH4 SH4A SH2A
lds.l @Rm+,FPUL
(Rm) -> FPUL, Rm+4 -> Rm
0100mmmm01010110
LS LS
1 1 1 1 1
1 1 1/2 1 2
SH2E SH3E SH4 SH4A SH2A
sts.l FPUL,@-Rn
Rn-4 -> Rn, FPUL -> (Rn)
0100nnnn01010010
CO LS
1 1 1 1 1
1 1 1/1 1 2
SH4 SH4A
frchg
If FPSCR.PR = 0: ~FPSCR.FR -> FPSCR.FR Else: Undefined Operation
1111101111111101
FE FE
1 1
1/4 1
SH4 SH4A SH2A
fschg
If FPSCR.PR = 0: ~FPSCR.SZ -> FPSCR.SZ Else: Undefined Operation
1111001111111101
FE FE
1 1 1
1/4 1 1
SH4A
fpchg
~FPSCR.PR -> FPSCR.PR
1111011111111101
FE
1
1

DSP Data Transfer Instructions

DSP
nopx
No operation
1111000*0*0*00**
1
1
DSP
movx.w @Ax,Dx
(Ax) -> MSW of Dx, 0 -> LSW of Dx
111100A*D*0*01**
1
1
DSP
movx.w @Ax+,Dx
(Ax) -> MSW of Dx, 0 -> LSW of Dx, Ax+2 -> Ax
111100A*D*0*10**
1
1
DSP
movx.w @Ax+Ix,Dx
(Ax) -> MSW of Dx, 0 -> LSW of Dx, Ax+Ix -> Ax
111100A*D*0*11**
1
1
DSP
movx.w Da,@Ax
MSW of Da -> (Ax)
111100A*D*1*01**
1
1
DSP
movx.w Da,@Ax+
MSW of Da -> (Ax), Ax+2 -> Ax
111100A*D*1*10**
1
1
DSP
movx.w Da,@Ax+Ix
MSW of Da -> (Ax), Ax+Ix -> Ax
111100A*D*1*11**
1
1
DSP
nopy
No Operation
111100*0*0*0**00
1
1
DSP
movy.w @Ay,Dy
(Ay) -> MSW of Dy, 0 -> LSW of Dy
111100*A*D*0**01
1
1
DSP
movy.w @Ay+,Dy
(Ay) -> MSW of Dy, 0 -> LSW of Dy, Ay+2 -> Ay
111100*A*D*0**10
1
1
DSP
movy.w @Ay+Iy,Dy
(Ay) -> MSW of Dy, 0 -> LSW of Dy, Ay+Iy -> Ay
111100*A*D*0**11
1
1
DSP
movy.w Da,@Ay
MSW of Da -> (Ay)
111100*A*D*1**01
1
1
DSP
movy.w Da,@Ay+
MSW of Da -> (Ay), Ay+2 -> Ay
111100*A*D*1**10
1
1
DSP
movy.w Da,@Ay+Iy
MSW of Da -> (Ay), Ay+Iy -> Ay
111100*A*D*1**11
1
1
DSP
movs.w @-As,Ds
As-2 -> As, (As) -> MSW of Ds, 0 -> LSW of Ds
111101AADDDD0000
1
1
DSP
movs.w @As,Ds
(As) -> MSW of Ds, 0 -> LSW of Ds
111101AADDDD0100
1
1
DSP
movs.w @As+,Ds
(As) -> MSW of Ds, 0 -> LSW of Ds, As+2 -> As
111101AADDDD1000
1
1
DSP
movs.w @As+Ix,Ds
(As) -> MSW of Ds, 0 -> LSW of DS, As+Ix -> As
111101AADDDD1100
1
1
DSP
movs.w Ds,@-As
As-2 -> As, MSW of Ds -> (As)
111101AADDDD0001
1
1
DSP
movs.w Ds,@As
MSW of Ds -> (As)
111101AADDDD0101
1
1
DSP
movs.w Ds,@As+
MSW of Ds -> (As), As+2 -> As
111101AADDDD1001
1
1
DSP
movs.w Ds,@As+Is
MSW of DS -> (As), As+Is -> As
111101AADDDD1101
1
1
DSP
movs.l @-As,Ds
As-4 -> As, (As) -> Ds
111101AADDDD0010
1
1
DSP
movs.l @As,Ds
(As) -> Ds
111101AADDDD0110
1
1
DSP
movs.l @As+,Ds
(As) -> Ds, As+4 -> As
111101AADDDD1010
1
1
DSP
movs.l @As+Is,Ds
(As) -> Ds, As+Is -> As
111101AADDDD1110
1
1
DSP
movs.l Ds,@-As
As-4 -> As, Ds -> (As)
111101AADDDD0011
1
1
DSP
movs.l Ds,@As
Ds -> (As)
111101AADDDD0111
1
1
DSP
movs.l Ds,@As+
Ds -> (As), As+4 -> As
111101AADDDD1011
1
1
DSP
movs.l Ds,@As+Is
Ds -> (As), As+Is -> As
111101AADDDD1111
1
1

DSP ALU Arithmetic Operation Instructions

DSP
pabs Sx,Dz
If Sx >= 0: Sx -> Dz If Sx < 0: 0 - Sx -> Dz
111110********** 10001000xx00zzzz
Update
1
1
DSP
pabs Sy,Dz
If Sy >= 0: Sy -> Dz If Sy < 0: 0 - Sy -> Dz
111110********** 1010100000yyzzzz
Update
1
1
DSP
padd Sx,Sy,Dz
Sx + Sy -> Dz
111110********** 10110001xxyyzzzz
Update
1
1
DSP
dct padd Sx,Sy,Dz
If DC = 1: Sx + Sy -> Dz Else: nop
111110********** 10110010xxyyzzzz
1
1
DSP
dcf padd Sx,Sy,Dz
If DC = 0: Sx + Sy -> Dz Else: nop
111110********** 10110011xxyyzzzz
1
1
DSP
padd Sx,Sy,Du pmuls Se,Sf,Dg
Sx + Sy -> Du MSW of Se * MSW of Sf -> Dg
111110********** 0111eeffxxyygguu
Update
1
1
DSP
paddc Sx,Sy,Dz
Sx + Sy + DC -> Dz
111110********** 10110000xxyyzzzz
Update
1
1
DSP
pclr Dz
0x00000000 -> Dz
111110********** 100011010000zzzz
Update
1
1
DSP
dct pclr Dz
If DC = 1: 0x00000000 -> Dz Else: nop
111110********** 100011100000zzzz
1
1
DSP
dcf pclr Dz
If DC = 0: 0x00000000 -> Dz Else: nop
111110********** 100011110000zzzz
1
1
DSP
pcmp Sx,Sy
Sx - Sy
111110********** 10000100xxyy0000
Update
1
1
DSP
pcopy Sx,Dz
Sx -> Dz
111110********** 11011001xx00zzzz
Update
1
1
DSP
pcopy Sy,Dz
Sy -> Dz
111110********** 1111100100yyzzzz
Update
1
1
DSP
dct pcopy Sx,Dz
If DC = 1: Sx -> Dz Else: nop
111110********** 11011010xx00zzzz
1
1
DSP
dct pcopy Sy,Dz
If DC = 1: Sy -> Dz Else: nop
111110********** 1111101000yyzzzz
1
1
DSP
dcf pcopy Sx,Dz
If DC = 0: Sx -> Dz Else: nop
111110********** 11011011xx00zzzz
1
1
DSP
dcf pcopy Sy,Dz
If DC = 0: Sy -> Dz Else: nop
111110********** 1111101100yyzzzz
1
1
DSP
pneg Sx,Dz
0 - Sx -> Dz
111110********** 11001001xx00zzzz
Update
1
1
DSP
pneg Sy,Dz
0 - Sy -> Dz
111110********** 1110100100yyzzzz
Update
1
1
DSP
dct pneg Sx,Dz
If DC = 1: 0 - Sx -> Dz Else: nop
111110********** 11001010xx00zzzz
1
1
DSP
dct pneg Sy,Dz
If DC = 1: 0 - Sy -> Dz Else: nop
111110********** 1110101000yyzzzz
1
1
DSP
dcf pneg Sx,Dz
If DC = 0: 0 - Sx -> Dz Else: nop
111110********** 11001011xx00zzzz
1
1
DSP
dcf pneg Sy,Dz
If DC = 0: 0 - Sy -> Dz Else: nop
111110********** 1110101100yyzzzz
1
1
DSP
psub Sx,Sy,Dz
Sx - Sy -> Dz
111110********** 10100001xxyyzzzz
Update
1
1
DSP
dct psub Sx,Sy,Dz
If DC = 1: Sx - Sy -> Dz Else: nop
111110********** 10100010xxyyzzzz
1
1
DSP
dcf psub Sx,Sy,Dz
If DC = 0: Sx - Sy -> Dz Else: nop
111110********** 10100011xxyyzzzz
1
1
DSP
psub Sx,Sy,Du pmuls Se,Sf,Dg
Sx - Sy -> Du MSW of Se * MSW of Sf -> Dg
111110********** 0110eeffxxyygguu
Update
1
1
DSP
psubc Sx,Sy,Dz
Sx - Sy - DC -> Dz
111110********** 10100000xxyyzzzz
Update
1
1
DSP
pdec Sx,Dz
MSW of Sx - 1 -> MSW of Dz, clear LSW of Dz
111110********** 10001001xx00zzzz
Update
1
1
DSP
pdec Sy,Dz
MSW of Sy - 1 -> MSW of Dz, clear LSW of Dz
111110********** 1010100100yyzzzz
Update
1
1
DSP
dct pdec Sx,Dz
If DC = 1: MSW of Sx - 1 -> MSW of DZ, clear LSW of Dz Else: nop
111110********** 10001010xx00zzzz
1
1
DSP
dct pdec Sy,Dz
If DC = 1: MSW of Sy - 1 -> MSW of DZ, clear LSW of Dz Else: nop
111110********** 1010101000yyzzzz
1
1
DSP
dcf pdec Sx,Dz
If DC = 0: MSW of Sx - 1 -> MSW of DZ, clear LSW of Dz Else: nop
111110********** 10001011xx00zzzz
1
1
DSP
dcf pdec Sy,Dz
If DC = 0: MSW of Sy - 1 -> MSW of DZ, clear LSW of Dz Else: nop
111110********** 1010101100yyzzzz
1
1
DSP
pinc Sx,Dz
MSW of Sy + 1 -> MSW of Dz, clear LSW of Dz
111110********** 10011001xx00zzzz
Update
1
1
DSP
pinc Sy,Dz
MSW of Sy + 1 -> MSW of Dz, clear LSW of Dz
111110********** 1011100100yyzzzz
Update
1
1
DSP
dct pinc Sx,Dz
If DC = 1: MSW of Sx + 1 -> MSW of Dz, clear LSW of Dz Else: nop
111110********** 10011010xx00zzzz
1
1
DSP
dct pinc Sy,Dz
If DC = 1: MSW of Sy + 1 -> MSW of Dz, clear LSW of Dz Else: nop
111110********** 1011101000yyzzzz
1
1
DSP
dcf pinc Sx,Dz
If DC = 0: MSW of Sx + 1 -> MSW of Dz, clear LSW of Dz Else: nop
111110********** 10011011xx00zzzz
1
1
DSP
dcf pinc Sy,Dz
If DC = 0: MSW of Sy + 1 -> MSW of Dz, clear LSW of Dz Else: nop
111110********** 1011101100yyzzzz
1
1
DSP
pdmsb Sx,Dz
Sx data MSB position -> MSW of Dz, clear LSW of Dz
111110********** 10011101xx00zzzz
Update
1
1
DSP
pdmsb Sy,Dz
Sy data MSB position -> MSW of Dz, clear LSW of Dz
111110********** 1011110100yyzzzz
Update
1
1
DSP
dct pdmsb Sx,Dz
If DC = 1: Sx data MSB position -> MSW of Dz, clear LSW of Dz Else: nop
111110********** 10011110xx00zzzz
1
1
DSP
dct pdmsb Sy,Dz
If DC = 1: Sy data MSB position -> MSW of Dz, clear LSW of Dz Else: nop
111110********** 1011111000yyzzzz
1
1
DSP
dcf pdmsb Sx,Dz
If DC = 0: Sx data MSB position -> MSW of Dz, clear LSW of Dz Else: nop
111110********** 10011111xx00zzzz
1
1
DSP
dcf pdmsb Sy,Dz
If DC = 0: Sy data MSB position -> MSW of Dz, clear LSW of Dz Else: nop
111110********** 1011111100yyzzzz
1
1
DSP
prnd Sx,Dz
Sx + 0x00008000 -> Dz, clear LSW of Dz
111110********** 10011000xx00zzzz
1
1
DSP
prnd Sy,Dz
Sy + 0x00008000 -> Dz, clear LSW of Dz
111110********** 1011100000yyzzzz
1
1

DSP ALU Logical Operation Instructions

DSP
pand Sx,Sy,Dz
Sx & Sy -> Dz, clear LSW of Dz
111110********** 10010101xxyyzzzz
Update
1
1
DSP
dct pand Sx,Sy,Dz
If DC = 1: Sx & Sy -> Dz, clear LSW of Dz Else: nop
111110********** 10010110xxyyzzzz
1
1
DSP
dcf pand Sx,Sy,Dz
If DC = 0: Sx & Sy -> Dz, clear LSW of Dz Else: nop
111110********** 10010111xxyyzzzz
1
1
DSP
por Sx,Sy,Dz
Sx | Sy -> Dz, clear LSW of Dz
111110********** 10110101xxyyzzzz
Update
1
1
DSP
dct por Sx,Sy,Dz
If DC = 1: Sx | Sy -> Dz, clear LSW of Dz Else: nop
111110********** 10110110xxyyzzzz
1
1
DSP
dcf por Sx,Sy,Dz
If DC = 0: Sx | Sy -> Dz, clear LSW of Dz Else: nop
111110********** 10110111xxyyzzzz
1
1
DSP
pxor Sx,Sy,Dz
Sx ^ Sy -> Dz, clear LSW of Dz
111110********** 10100101xxyyzzzz
Update
1
1
DSP
dct pxor Sx,Sy,Dz
If DC = 1: Sx ^ Sy -> Dz, clear LSW of Dz Else: nop
111110********** 10100110xxyyzzzz
1
1
DSP
dcf pxor Sx,Sy,Dz
If DC = 0: Sx ^ Sy -> Dz, clear LSW of Dz Else: nop
111110********** 10100111xxyyzzzz
1
1

DSP Fixed Decimal Point Multiplication Instructions

DSP
pmuls Se,Sf,Dg
MSW of Se * MSW of Sf -> Dg
111110********** 0100eeff0000gg00
1
1

DSP Shift Operation Instructions

DSP
psha Sx,Sy,Dz
If Sy >= 0: Sx << Sy -> Dz If Sy < 0: Sx >> Sy -> Dz
111110********** 10010001xxyyzzzz
Update
1
1
DSP
dct psha Sx,Sy,Dz
If DC = 1 & Sy >= 0: Sx << Sy -> Dz If DC = 1 & Sy < 0: Sx >> Sy -> Dz If DC = 0: nop
111110********** 10010010xxyyzzzz
1
1
DSP
dcf psha Sx,Sy,Dz
If DC = 0 & Sy >= 0: Sx << Sy -> Dz If DC = 0 & Sy < 0: Sx >> Sy -> Dz If DC = 1: nop
111110********** 10010011xxyyzzzz
1
1
DSP
psha #imm,Dz
If imm >= 0: Dz << imm -> Dz If imm < 0: Dz >> imm -> Dz
111110********** 00000iiiiiiizzzz
Update
1
1
DSP
pshl Sx,Sy,Dz
If Sy >= 0: Sx << Sy -> Dz, clear LSW of Dz If Sy < 0: Sx >> Sy -> Dz, clear LSW of Dz
111110********** 10000001xxyyzzzz
Update
1
1
DSP
dct pshl Sx,Sy,Dz
If DC = 1 & Sy >= 0: Sx << Sy -> Dz, clear LSW of Dz If DC = 1 & Sy < 0: Sx >> Sy -> Dz, clear LSW of Dz If DC = 0: nop
111110********** 10000010xxyyzzzz
1
1
DSP
dcf pshl Sx,Sy,Dz
If DC = 0 & Sy >= 0: Sx << Sy -> Dz, clear LSW of Dz If DC = 0 & Sy < 0: Sx >> Sy -> Dz, clear LSW of Dz If DC = 1: nop
111110********** 10000011xxyyzzzz
1
1
DSP
pshl #imm,Dz
If imm >= 0: Dz << imm -> Dz, clear LSW of Dz If imm < 0: Dz >> imm, clear LSW of Dz
111110********** 00010iiiiiiizzzz
Update
1
1

DSP System Control Instructions

DSP
plds Dz,MACH
Dz -> MACH
111110********** 111011010000zzzz
1
1
DSP
plds Dz,MACL
Dz -> MACL
111110********** 111111010000zzzz
1
1
DSP
dct plds Dz,MACH
If DC = 1: Dz -> MACH Else: nop
111110********** 111011100000zzzz
1
1
DSP
dct plds Dz,MACL
If DC = 1: Dz -> MACL Else: nop
111110********** 111111100000zzzz
1
1
DSP
dcf plds Dz,MACH
If DC = 0: Dz -> MACH Else: nop
111110********** 111011110000zzzz
1
1
DSP
dcf plds Dz,MACL
If DC = 0: Dz -> MACL Else: nop
111110********** 111111110000zzzz
1
1
DSP
psts MACH,Dz
MACH -> Dz
111110********** 110011010000zzzz
1
1
DSP
psts MACL,Dz
MACL -> Dz
111110********** 110111010000zzzz
1
1
DSP
dct psts MACH,Dz
If DC = 1: MACH -> Dz Else: nop
111110********** 110011100000zzzz
1
1
DSP
dct psts MACL,Dz
If DC = 1: MACL -> Dz Else: nop
111110********** 110111100000zzzz
1
1
DSP
dcf psts MACH,Dz
If DC = 0: MACH -> Dz Else: nop
111110********** 110011110000zzzz
1
1
DSP
dcf psts MACL,Dz
If DC = 0: MACL -> Dz Else: nop
111110********** 110111110000zzzz
1
1